Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only)
Page 283
Abstract
This paper presents the implementation of a high resolution time-to-digital converter (TDC) on a dynamically reconfigurable FPGA. The TDC architecture is based on the Vernier method using two ring oscillators with slightly different frequencies. The proposed oscillators can be calibrated with picoseconds resolution by taking advantage of partial reconfiguration, and moreover recalibrated over time. The results obtained on a Xilinx Virtex-II Pro FPGA show that the proposed TDC implementation can achieve unprecedented resolutions (on FPGA) as low as 5ps and precisions up to 25ps.
References
[1]
Kinniment, D.J., Dike, C.E., Heron, K., and Russel, G. 2007. Measuring deep metastability and its effect on synchronizer performance. IEEE Transactions on VLSI Systems, vol. 15, Sept. 2007, 1028--1039.
[2]
Yousif, A.S., and Haslett, J.W., A fine resolution TDC architecture for next generation PET imaging. IEEE Transactions on nuclear science, vol. 54, Oct. 2007, 1574--1582.
[3]
Lee, M., Abidi, A.A., A 9b, 1.25ps resolution coarse-fine time-to-digital converter in 90nm CMOS that amplifies a time residue. IEEE Journal of solid-state circuits, vol. 43, Apr. 2008, 769--777.
[4]
Song, J., An, Q., Liu, S., A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays. IEEE Transactions on nuclear science, vol. 53, Feb. 2006, 236--241.
[5]
Favi, C., Charbon, E., A 17ps time-to-digital converter implemented in 65nm FPGA technology. In Proceedings of the FPGA'09 ACM/SIGDA International Symposium on FPGA (Monterey, CA, February 22-24, 2009).
[6]
Minas, M., Kinniment, D., Heron, K., Russel, G., A high resolution flash time-to-digital converter taking into account process variability. In 13th IEEE Symposium on Asynchronous Circuits and Systems, Mar. 2007, 163--174.
[7]
Amiri, A., Boukadoum, M., Khouas, A., A multihit time-to-digital converter architecture on FPGA. IEEE Transactions on Instrumentation and Measurement, vol. 58, no. 3, Mar. 2009, 530--340.
[8]
Jin, K-C., Moon, M-K., TDC module for time-of-flight. In IEEE Conference Rec. NSS., vol. 1, 2003, 177--181.
[9]
Lin, M-C., Tsai, G-R., Liu, C-Y., and Chu, S-S. FPGA-based high area efficient time-to-digital IP design. In Proceeding of IEEE TENCON 2006 Conference, Nov. 2006, 1-4.
[10]
Kalisz, J. Review of methods for time interval measurement with picosecond resolution. Metrologia, vol. 41, 2004, 17--32.
[11]
Dyer, S.A. 2001 Wiley survey of Instrumentation and Measurement. Wiley-IEEE Press, 734--741.
[12]
Bergeron, E., Feeley, M., Daigneault, M-A., David, J.P., Using dynamic reconfiguration to implement high-resolution programmable delays on an FPGA. In Proceedings of IEEE Northeast Workshop on Circuit and Systems and TAISA Conference 2008, Jun. 2008, 265--268.
[13]
Strogatz, S.H., Exploring complex networks. Nature, vol. 410, Mar. 2001, 268--276.
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February 2010
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Published: 21 February 2010
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