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Architectural support for translation table management in large address space machines

Authors:

Jerry Huck,

Jim HaysAuthors Info & Claims

ISCA '93: Proceedings of the 20th annual international symposium on computer architecture

Pages 39 - 50

https://doi.org/10.1145/165123.165128

Published: 01 May 1993 Publication History

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Abstract

Virtual memory page translation tables provide mappings from virtual to physical addresses. When the hardware controlled Translation Lookaside Buffers (TLBs) do not contain a translation, these tables provide the translation. Approaches to the structure and management of these tables vary from full hardware implementations to complete software based algorithms.

The size of the virtual address space used by processes is rapidly growing beyond 32 bits of address. As the utilized address space increases, new problems and issues surface. Traditional methods for managing the page translation tables are inappropriate for large address space architectures.

The Hashed Page Table (HPT), described here, provides a very fast and space efficient translation table that reduces overhead by splitting TLB management responsibilities between hardware and software. Measurements demonstrate its applicability to a diverse range of operating systems and workloads and, in particular, to large virtual address space machines. In simulations of over 4 billion instructions, improvement of 5 to 10% were observed.

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Cited By

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Gosakan KHan JKuszmaul WMubarek IMukherjee NSriram KTagliavini GWest EBender MBhattacharjee AConway AFarach-Colton MGandhi JJohnson RKannan SPorter DAamodt TJerger NSwift M(2023)Mosaic Pages: Big TLB Reach with Small PagesProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3582016.3582021(433-448)Online publication date: 25-Mar-2023
https://dl.acm.org/doi/10.1145/3582016.3582021
Zhao KXue KWang ZSchatzberg DYang LManousis AWeiner JVan Riel RSharma BTang CSkarlatos DSolihin YHeinrich M(2023)Contiguitas: The Pursuit of Physical Memory Contiguity in DatacentersProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589079(1-15)Online publication date: 17-Jun-2023
https://dl.acm.org/doi/10.1145/3579371.3589079
Stojkovic JMantri NSkarlatos DXu TTorrellas J(2023)Memory-Efficient Hashed Page Tables2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071061(1221-1235)Online publication date: Mar-2023
https://doi.org/10.1109/HPCA56546.2023.10071061
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Index Terms

Architectural support for translation table management in large address space machines
1. Hardware
  1. Communication hardware, interfaces and storage
  2. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory
2. Information systems
  1. Information storage systems
    1. Record storage systems
      1. Record storage alternatives
        Hashed file organization

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Architectural support for translation table management in large address space machines
Special Issue: Proceedings of the 20th annual international symposium on Computer architecture (ISCA '93)

Virtual memory page translation tables provide mappings from virtual to physical addresses. When the hardware controlled Translation Lookaside Buffers (TLBs) do not contain a translation, these tables provide the translation. Approaches to the structure ...
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Information

Published In

ISCA '93: Proceedings of the 20th annual international symposium on computer architecture

June 1993

361 pages

ISBN:0818638109

DOI:10.1145/165123

Chairman:
Alan Jay Smith

ACM SIGARCH Computer Architecture News Volume 21, Issue 2
Special Issue: Proceedings of the 20th annual international symposium on Computer architecture (ISCA '93)
May 1993
348 pages
ISSN:0163-5964
DOI:10.1145/173682
Editor:
Doug DeGroot
Texas Instruments Inc., Dallas, TX
Issue’s Table of Contents

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1993

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20ISCA93

Sponsor:

SIGARCH
IEEE-CS
IEEE-CS\TCCA

20ISCA93: 20th International Symposium on Computer Architecture

May 16 - 19, 1993

California, San Diego, USA

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

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Cited By

View all

Gosakan KHan JKuszmaul WMubarek IMukherjee NSriram KTagliavini GWest EBender MBhattacharjee AConway AFarach-Colton MGandhi JJohnson RKannan SPorter DAamodt TJerger NSwift M(2023)Mosaic Pages: Big TLB Reach with Small PagesProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3582016.3582021(433-448)Online publication date: 25-Mar-2023
https://dl.acm.org/doi/10.1145/3582016.3582021
Zhao KXue KWang ZSchatzberg DYang LManousis AWeiner JVan Riel RSharma BTang CSkarlatos DSolihin YHeinrich M(2023)Contiguitas: The Pursuit of Physical Memory Contiguity in DatacentersProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589079(1-15)Online publication date: 17-Jun-2023
https://dl.acm.org/doi/10.1145/3579371.3589079
Stojkovic JMantri NSkarlatos DXu TTorrellas J(2023)Memory-Efficient Hashed Page Tables2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071061(1221-1235)Online publication date: Mar-2023
https://doi.org/10.1109/HPCA56546.2023.10071061
Fatima ALiu SSeemakhupt KAusavarungnirun RKhan S(2023)vPIM: Efficient Virtual Address Translation for Scalable Processing-in-Memory Architectures2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247745(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247745
Stojkovic JSkarlatos DKokolis AXu TTorrellas JFalsafi BFerdman MLu SWenisch T(2022)Parallel virtualized memory translation with nested elastic cuckoo page tablesProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507720(84-97)Online publication date: 28-Feb-2022
https://dl.acm.org/doi/10.1145/3503222.3507720
Vavouliotis GAlvarez LGrot BJiménez DCasas M(2021)Morrigan: A Composite Instruction TLB PrefetcherMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480049(1138-1153)Online publication date: 18-Oct-2021
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Vavouliotis GAlvarez LKarakostas VNikas KKoziris NJimenez DCasas M(2021)Exploiting Page Table Locality for Agile TLB Prefetching2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA52012.2021.00016(85-98)Online publication date: Jun-2021
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Skarlatos DKokolis AXu TTorrellas JLarus JCeze LStrauss K(2020)Elastic Cuckoo Page TablesProceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3373376.3378493(1093-1108)Online publication date: 9-Mar-2020
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Hetland CTziantzioulis GSuchy BHale KHardavellas NDinda P(2019)Prospects for Functional Address Translation2019 IEEE 27th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)10.1109/MASCOTS.2019.00047(370-383)Online publication date: Oct-2019
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Merrifield TTaheri H(2017)Performance Implications of Extended Page Tables on Virtualized x86 ProcessorsACM SIGOPS Operating Systems Review10.1145/3139645.313965251:1(38-47)Online publication date: 11-Sep-2017
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