research-article

SystemC-based modelling, seamless refinement, and synthesis of a JPEG 2000 decoder

Authors:

Anne-Marie FouilliartAuthors Info & Claims

DATE '08: Proceedings of the conference on Design, automation and test in Europe

Pages 128 - 133

https://doi.org/10.1145/1403375.1403409

Published: 10 March 2008 Publication History

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Abstract

This paper will exemplarily describe and evaluate the OSSS methodology for embedded hardware/software systems and its use in a JPEG 2000 decoder case-study. The OSSS approach defines a design flow starting from an Application Model providing a rich subset of SystemC™/C⁺⁺ augmented with specific OSSS language concepts. It can be used to identify the most promising parallel structure by comparing different design alternatives. A clearly defined refinement process leads to the Virtual Target Architecture (VTA) Model. These refinements enable an analysis of the system behaviour at cycle-accurate granularity and support the exploration of different target architectures for the JPEG 2000 decoder. VTA models can be used as direct input for the FOSSY synthesis tool, which performs an automatic transformation into implementation models; that is to generate VHDL code for hardware, C/C⁺⁺ for software, and platform configuration files for the target technology.

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Cited By

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Ben Atitallah AKammoun MAli KBen Atitallah R(2020)An FPGA comparative study of high‐level and low‐level combined designs for HEVC intra, inverse quantization, and IDCT/IDST 2D modulesInternational Journal of Circuit Theory and Applications10.1002/cta.279048:8(1274-1290)Online publication date: 14-Apr-2020
https://doi.org/10.1002/cta.2790
Liu XChen YNguyen TGurumani SRupnow KChen DChen DGreene J(2016)High Level Synthesis of Complex ApplicationsProceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2847263.2847274(224-233)Online publication date: 21-Feb-2016
https://dl.acm.org/doi/10.1145/2847263.2847274
Muck TFrohlich A(2012)On AOP techniques for C++-based HW/SW component implementation2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)10.1109/ICECS.2012.6463690(536-539)Online publication date: Dec-2012
https://doi.org/10.1109/ICECS.2012.6463690
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Index Terms

SystemC-based modelling, seamless refinement, and synthesis of a JPEG 2000 decoder
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems
2. Hardware

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Information

Published In

DATE '08: Proceedings of the conference on Design, automation and test in Europe

March 2008

1575 pages

ISBN:9783981080131

DOI:10.1145/1403375

General Chair:
Donatella Sciuto
Politecnico di Milano, Italy

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 March 2008

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Research-article

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DATE '08

Sponsor:

EDAA
SIGDA
The Russian Academy of Sciences

DATE '08: Design, Automation and Test in Europe

March 10 - 14, 2008

Munich, Germany

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Citations

Cited By

View all

Ben Atitallah AKammoun MAli KBen Atitallah R(2020)An FPGA comparative study of high‐level and low‐level combined designs for HEVC intra, inverse quantization, and IDCT/IDST 2D modulesInternational Journal of Circuit Theory and Applications10.1002/cta.279048:8(1274-1290)Online publication date: 14-Apr-2020
https://doi.org/10.1002/cta.2790
Liu XChen YNguyen TGurumani SRupnow KChen DChen DGreene J(2016)High Level Synthesis of Complex ApplicationsProceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2847263.2847274(224-233)Online publication date: 21-Feb-2016
https://dl.acm.org/doi/10.1145/2847263.2847274
Muck TFrohlich A(2012)On AOP techniques for C++-based HW/SW component implementation2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)10.1109/ICECS.2012.6463690(536-539)Online publication date: Dec-2012
https://doi.org/10.1109/ICECS.2012.6463690
Flor JMuck TFrohlich A(2011)High-level design and synthesis of a resource scheduler2011 18th IEEE International Conference on Electronics, Circuits, and Systems10.1109/ICECS.2011.6122379(736-739)Online publication date: Dec-2011
https://doi.org/10.1109/ICECS.2011.6122379
Mueller WHe DMischkalla FWegele ALarkham AWhiston PPeñil PVillar EMitas NKritharidis DAzcarate FCarballeda M(2011)The SATURN Approach to SysML-Based HW/SW CodesignVLSI 2010 Annual Symposium10.1007/978-94-007-1488-5_9(151-164)Online publication date: 8-Sep-2011
https://doi.org/10.1007/978-94-007-1488-5_9
YOON SHUANG MSEO SOCHI HPARK S(2010)A Fast Architecture Exploration Method for High Throughput IEEE 802.11e MAC Implementation Using SystemCIEICE Transactions on Communications10.1587/transcom.E93.B.2833E93-B:10(2833-2836)Online publication date: 2010
https://doi.org/10.1587/transcom.E93.B.2833
Zaidi YGrimm CHaase J(2010)On mixed abstraction, languages, and simulation approach to refinement with systemC AMSEURASIP Journal on Embedded Systems10.1155/2010/4893652010(5-5)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1155/2010/489365
Mueller WHe DMischkalla FWegele AWhiston PPenil PVillar EMitas NKritharidis DAzcarate FCarballeda M(2010)The SATURN Approach to SysML-Based HW/SW CodesignProceedings of the 2010 IEEE Annual Symposium on VLSI10.1109/ISVLSI.2010.95(506-511)Online publication date: 5-Jul-2010
https://dl.acm.org/doi/10.1109/ISVLSI.2010.95
Chen WHan XDomer R(2010)ESL design and multi-core validation using the System-on-Chip Environment2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)10.1109/HLDVT.2010.5496646(142-147)Online publication date: Jun-2010
https://doi.org/10.1109/HLDVT.2010.5496646
Dömer RGerstlauer APeng JShin DCai LYu HAbdi SGajski D(2008)System-on-chip environmentEURASIP Journal on Embedded Systems10.1155/2008/6479532008(1-13)Online publication date: 1-Jan-2008
https://dl.acm.org/doi/10.1155/2008/647953

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