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Accelerating two-dimensional page walks for virtualized systems

Published: 01 March 2008 Publication History

Abstract

Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. Nested paging complements existing page walk hardware to form a two-dimensional (2D) page walk, which reduces the need for hypervisor intervention in guest page table management. However, the extra dimension also increases the maximum number of architecturally-required page table references.
This paper presents an in-depth examination of the 2D page table walk overhead and options for decreasing it. These options include using the AMD Opteron processor's page walk cache to exploit the strong reuse of page entry references. For a mix of server and SPEC benchmarks, the presented results show a 15%-38% improvement in guest performance by extending the existing page walk cache to also store the nested dimension of the 2D page walk. Caching nested page table translations and skipping multiple page entry references produce an additional 3%-7% improvement.
Much of the remaining 2D page walk overhead is due to low-locality nested page entry references, which result in additional memory hierarchy misses. By using large pages, the hypervisor can eliminate many of these long-latency accesses and further improve the guest performance by 3%-22%.

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Published In

cover image ACM Conferences
ASPLOS XIII: Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
March 2008
352 pages
ISBN:9781595939586
DOI:10.1145/1346281
  • cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 43, Issue 3
    ASPLOS '08
    March 2008
    339 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/1353536
    Issue’s Table of Contents
  • cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 36, Issue 1
    ASPLOS '08
    March 2008
    339 pages
    ISSN:0163-5964
    DOI:10.1145/1353534
    Issue’s Table of Contents
  • cover image ACM SIGOPS Operating Systems Review
    ACM SIGOPS Operating Systems Review  Volume 42, Issue 2
    ASPLOS '08
    March 2008
    339 pages
    ISSN:0163-5980
    DOI:10.1145/1353535
    Issue’s Table of Contents
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Published: 01 March 2008

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Author Tags

  1. AMD
  2. TLB
  3. hypervisor
  4. memory management
  5. nested paging
  6. page walk caching
  7. virtual machine monitor
  8. virtualization

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ASPLOS XIII Paper Acceptance Rate 31 of 127 submissions, 24%;
Overall Acceptance Rate 535 of 2,713 submissions, 20%

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  • (2024)SmartNIC Security Isolation in the Cloud with S-NICProceedings of the Nineteenth European Conference on Computer Systems10.1145/3627703.3650071(851-869)Online publication date: 22-Apr-2024
  • (2023)Accelerating Extra Dimensional Page Walks for Confidential ComputingProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614293(654-669)Online publication date: 28-Oct-2023
  • (2023)Tailor-made Virtualization Monitor Design for CPU Virtualization on LEON ProcessorsACM Transactions on Embedded Computing Systems10.1145/358470222:4(1-32)Online publication date: 17-Feb-2023
  • (2023)Mosaic Pages: Big TLB Reach with Small PagesProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3582016.3582021(433-448)Online publication date: 25-Mar-2023
  • (2023)Contiguitas: The Pursuit of Physical Memory Contiguity in DatacentersProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589079(1-15)Online publication date: 17-Jun-2023
  • (2023)Making Dynamic Page Coalescing Effective on Virtualized CloudsProceedings of the Eighteenth European Conference on Computer Systems10.1145/3552326.3567487(298-313)Online publication date: 8-May-2023
  • (2023)CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space ExplorationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.330283731:11(1713-1726)Online publication date: Nov-2023
  • (2023)HugeGPT: Storing Guest Page Tables on Host Huge Pages to Accelerate Address Translation2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT58117.2023.00014(62-73)Online publication date: 21-Oct-2023
  • (2023)Memory-Efficient Hashed Page Tables2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071061(1221-1235)Online publication date: Feb-2023
  • (2023)Disaggregated Memory in the Datacenter: A SurveyIEEE Access10.1109/ACCESS.2023.325040711(20688-20712)Online publication date: 2023
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