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An instruction-level performance analysis of the Multiflow TRACE 14/300

Authors:

Michael A. Schuette,

John P. ShenAuthors Info & Claims

MICRO 24: Proceedings of the 24th annual international symposium on Microarchitecture

Pages 2 - 11

https://doi.org/10.1145/123465.123468

Published: 01 September 1991 Publication History

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Cited By

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August D(2010)Branch PredicationSpeculative Execution in High Performance Computer Architectures10.1201/9781420035155.ch5(109-133)Online publication date: 14-Jan-2010
https://doi.org/10.1201/9781420035155.ch5
Schuette MShen J(1994)Exploiting Instruction-Level Parallelism for Integrated Control-Flow MonitoringIEEE Transactions on Computers10.1109/12.26211843:2(129-140)Online publication date: 1-Feb-1994
https://dl.acm.org/doi/10.1109/12.262118
Hwu WMahlke SChen WChang PWarter NBringmann ROuellette RHank RKiyohara THaab GHolm JLavery D(1993)The superblockThe Journal of Supercomputing10.1007/BF012051857:1-2(229-248)Online publication date: 1-May-1993
https://dl.acm.org/doi/10.1007/BF01205185
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Index Terms

An instruction-level performance analysis of the Multiflow TRACE 14/300
1. General and reference
  1. Cross-computing tools and techniques
    1. Performance
2. Software and its engineering
  1. Software notations and tools
    1. Compilers

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Published In

MICRO 24: Proceedings of the 24th annual international symposium on Microarchitecture

September 1991

223 pages

ISBN:0897914600

DOI:10.1145/123465

Chairman:
Yashwant K. Malaiya

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 September 1991

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Cited By

View all

August D(2010)Branch PredicationSpeculative Execution in High Performance Computer Architectures10.1201/9781420035155.ch5(109-133)Online publication date: 14-Jan-2010
https://doi.org/10.1201/9781420035155.ch5
Schuette MShen J(1994)Exploiting Instruction-Level Parallelism for Integrated Control-Flow MonitoringIEEE Transactions on Computers10.1109/12.26211843:2(129-140)Online publication date: 1-Feb-1994
https://dl.acm.org/doi/10.1109/12.262118
Hwu WMahlke SChen WChang PWarter NBringmann ROuellette RHank RKiyohara THaab GHolm JLavery D(1993)The superblockThe Journal of Supercomputing10.1007/BF012051857:1-2(229-248)Online publication date: 1-May-1993
https://dl.acm.org/doi/10.1007/BF01205185
Mahlke SChen WGyllenhaal JHwu W(1992)Compiler code transformations for superscalar-based high performance systemsProceedings of the 1992 ACM/IEEE conference on Supercomputing10.5555/147877.148138(808-817)Online publication date: 1-Dec-1992
https://dl.acm.org/doi/10.5555/147877.148138
Mahlke SChen WGyllenhaal JHwu WChang PKiyohara T(1992)Compiler code transformations for superscalar-based high-performance systemsProceedings Supercomputing '9210.1109/SUPERC.1992.236682(808-817)Online publication date: 1992
https://doi.org/10.1109/SUPERC.1992.236682

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Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading

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Enhancing instruction level parallelism through compiler-controlled speculation