Article

Free access

Measurement of memory access contentions in multiple vector processor systems

Authors:

Ingrid Y. Bucher,

Margaret L. SimmonsAuthors Info & Claims

Supercomputing '91: Proceedings of the 1991 ACM/IEEE conference on Supercomputing

Pages 806 - 817

https://doi.org/10.1145/125826.126197

Published: 01 August 1991 Publication History

PDF eReader

References

[1]

I.Y. Bucher and D. A. Calahan, "Access Conflicts in Multiprocessor Memories: Queueing Models and Simulation Studies," Proc. 1990 International Conf. on Supercomputing, pp. 428-438, ACM Press, 1987.

Digital Library

Google Scholar

[2]

I.Y. Bucher and D. A. Calahan, "Models of Access Delays in Multiprocessor Memories," to be published in IEEE Transactions on Parallel and Distributed Systems.

Digital Library

Google Scholar

[3]

Cray Research, Inc., CRAY X-MP Computer Systems Hardware Manual, "Four Processor Mainframe Reference Manual," #HR-0097 (1985).

Google Scholar

[4]

Cray Research, Inc., CRAY Y-MP Hardware Manual, "CRAY Y-MP System Programmer Reference Manual," #CSM-0400-000 (1988).

Google Scholar

[5]

Robert Numrich, "The CRAY-2 Common Memory," Cray Research Inc. internal report, #HN-2043, (1988).

Google Scholar

[6]

J.J. Dongarra and S. C. Eisenstadt, "Squeezing the Most Out of an Algorithm in Cray Fortran," ACM Trans. Math. Software 10, pp. 221-230 (1984).

Digital Library

Google Scholar

[7]

I.Y. Bucher and M. L. Simmons, "A Close Look at Vector Performance of Register-to-Register Vector Computers and a New Model," Proceedings of the 1987 ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, pp. 39-45, ACM Press, 1987.

Digital Library

Google Scholar

[8]

I.Y. Bucher, "The Computational Speed of Supercomputers," Proceedings of the 1983 ACM SIG- METRICS Conference on Measurement and Modeling of Computer Systems, p. 151, ACM Press, 1983; reprinted in Supercomputers: Design and Applications, K. Hwang, Editor, IEEE Computer Society Press, 1984.

Digital Library

Google Scholar

[9]

D.A. Calahan and D. H. Bailey, "Measurement and Analysis of Memory Conflicts in Vector Multiprocessors," in Performance Evaluation of Supercomputers, J. L. Martin, Ed., Elsevier, 1988.

Google Scholar

[10]

D. T. Harper III and J. R. Jump, "Vector Access Performance in Parallel Memories Using a Skewed Storage Scheme," IEEE Trans. Comput., C-36, pp. 1440-1449 (1987).

Digital Library

Google Scholar

[11]

A. Norton and E. Melton, " A Class of Boolean Transformations for Conflict-Free Power-of-Two Stride Access," in Proc. Int. Conf. Parallel Processing 1987, pp. 247-254, 1EEE Computer Society Press, 1987.

Google Scholar

[12]

R. Raghavan and J. P. Hayes, "On Randomly Interleaved Memories," in Supercomputing '90, pp. 49- 58, IEEE Computer Society Press, 1990.

Digital Library

Google Scholar

Cited By

View all

Sun TYang Q(1999)A Comparative Analysis of Cache Designs for Vector ProcessingIEEE Transactions on Computers10.1109/12.75499948:3(331-344)Online publication date: 1-Mar-1999
https://dl.acm.org/doi/10.1109/12.754999
Blelloch GGibbons PMatias YZagha M(1997)Accounting for Memory Bank Contention and Delay in High-Bandwidth MultiprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/71.6154408:9(943-958)Online publication date: 1-Sep-1997
https://dl.acm.org/doi/10.1109/71.615440
Charny B(1996)Matrix Partitioning on a Virtual Shared Memory Parallel MachineIEEE Transactions on Parallel and Distributed Systems10.1109/71.4946297:4(343-355)Online publication date: 1-Apr-1996
https://dl.acm.org/doi/10.1109/71.494629
Show More Cited By

Index Terms

Measurement of memory access contentions in multiple vector processor systems

Recommendations

Inherent Limitations on Disjoint-Access Parallel Implementations of Transactional Memory
Special Issue: Parallelism in Algorithms and Architectures

Transactional memory (TM) is a popular approach for alleviating the difficulty of programming concurrent applications; TM guarantees that a transaction, consisting of a sequence of operations, appear to be executed atomically. Two fundamental properties ...
Minimizing Conflicts Between Vector Streams in Interleaved Memory Systems

The performance of a vector processor accessing vectors placed in memory is strongly dependent on the conflicts produced in the memory subsystem. These conflicts delay the task of the functional units. There can be conflicts between elements of the same ...
Access order to avoid inter-vector-conflicts in complex memory systems
IPPS '95: Proceedings of the 9th International Symposium on Parallel Processing

The performance of a vector processor accessing vectors is strongly dependent on the conflicts produced in the memory subsystem. The concurrent memory access of several vector streams causes inter-conflicts between the references of different vectors. ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

Supercomputing '91: Proceedings of the 1991 ACM/IEEE conference on Supercomputing

August 1991

920 pages

ISBN:0897914597

DOI:10.1145/125826

Conference Chair:
Ray Elliott

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 August 1991

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

SC '91

Sponsor:

SIGARCH
IEEE-CS

SC '91: International Conference for High Performance Computing, Networking, Storage and Analysis

November 18 - 22, 1991

New Mexico, Albuquerque, USA

Acceptance Rates

Supercomputing '91 Paper Acceptance Rate 83 of 215 submissions, 39%;

Overall Acceptance Rate 1,516 of 6,373 submissions, 24%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

12
Total Citations
View Citations
293
Total Downloads

Downloads (Last 12 months)43
Downloads (Last 6 weeks)4

Reflects downloads up to 20 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Sun TYang Q(1999)A Comparative Analysis of Cache Designs for Vector ProcessingIEEE Transactions on Computers10.1109/12.75499948:3(331-344)Online publication date: 1-Mar-1999
https://dl.acm.org/doi/10.1109/12.754999
Blelloch GGibbons PMatias YZagha M(1997)Accounting for Memory Bank Contention and Delay in High-Bandwidth MultiprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/71.6154408:9(943-958)Online publication date: 1-Sep-1997
https://dl.acm.org/doi/10.1109/71.615440
Charny B(1996)Matrix Partitioning on a Virtual Shared Memory Parallel MachineIEEE Transactions on Parallel and Distributed Systems10.1109/71.4946297:4(343-355)Online publication date: 1-Apr-1996
https://dl.acm.org/doi/10.1109/71.494629
Peiron MValero MAyguadé ELang T(1995)Vector multiprocessors with arbitrated memory accessACM SIGARCH Computer Architecture News10.1145/225830.22443523:2(243-252)Online publication date: 1-May-1995
https://dl.acm.org/doi/10.1145/225830.224435
Peiron MValero MAyguadé ELang TPatterson D(1995)Vector multiprocessors with arbitrated memory accessProceedings of the 22nd annual international symposium on Computer architecture10.1145/223982.224435(243-252)Online publication date: 1-Jul-1995
https://dl.acm.org/doi/10.1145/223982.224435
Yang QYang T(1995)A Memory Interference Model for Regularly Patterned Multiple Stream Vector AccessesIEEE Transactions on Parallel and Distributed Systems10.1109/71.3823206:5(520-530)Online publication date: 1-May-1995
https://dl.acm.org/doi/10.1109/71.382320
Tong Sun Qing Yang (1994)Performance of SPEC92 on prime-mapped vector cacheProceedings of the 1994 6th IEEE Symposium on Parallel and Distributed Processing10.1109/SPDP.1994.346121(569-576)Online publication date: 26-Oct-1994
https://dl.acm.org/doi/10.1109/SPDP.1994.346121
Numrich R(1992)Memory contention for shared memory vector multiprocessorsProceedings of the 1992 ACM/IEEE conference on Supercomputing10.5555/147877.148018(316-325)Online publication date: 1-Dec-1992
https://dl.acm.org/doi/10.5555/147877.148018
Numrich R(1992)Memory contention for shared memory vector multiprocessorsProceedings Supercomputing '9210.1109/SUPERC.1992.236671(316-325)Online publication date: 1992
https://doi.org/10.1109/SUPERC.1992.236671
Bucher ICalahan D(1992)Models of Access Delays in Multiprocessor MemoriesIEEE Transactions on Parallel and Distributed Systems10.1109/71.1392013:3(270-280)Online publication date: 1-May-1992
https://dl.acm.org/doi/10.1109/71.139201
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Inherent Limitations on Disjoint-Access Parallel Implementations of Transactional Memory

Minimizing Conflicts Between Vector Streams in Interleaved Memory Systems

Access order to avoid inter-vector-conflicts in complex memory systems