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Performance pathologies in hardware transactional memory

Published: 09 June 2007 Publication History

Abstract

Hardware Transactional Memory (HTM) systems reflect choices from three key design dimensions: conflict detection, version management, and conflict resolution. Previously proposed HTMs represent three points in this design space: lazy conflict detection, lazy version management, committer wins (LL); eager conflict detection, lazy version management, requester wins (EL); and eager conflict detection, eager version management, and requester stalls with conservative deadlock avoidance (EE). To isolate the effects of these high-level design decisions, we develop a common framework that abstracts away differences in cache write policies, interconnects, and ISA to compare these three design points. Not surprisingly, the relative performance of these systems depends on the workload. Under light transactional loads they perform similarly, but under heavy loads they differ by up to 80%. None of the systems performs best on all of our benchmarks. We identify seven performance pathologies-interactions between workload and system that degrade performance-as the root cause of many performance differences: FriendlyFire, StarvingWriter, SerializedCommit, FutileStall, StarvingElder, RestartConvoy, and DuelingUpgrades. We discuss when and on which systems these pathologies can occur and show that they actually manifest within TM workloads. The insight provided by these pathologies motivated four enhanced systems that often significantly reduce transactional memory overhead. Importantly, by avoiding transaction pathologies, each enhanced system performs well across our suite of benchmarks.

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  • (2022)Metasystem Pathologies in Complex System GovernanceComplex System Governance10.1007/978-3-030-93852-9_9(241-282)Online publication date: 19-Apr-2022
  • (2021)DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional MemoryIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.3085210(1-1)Online publication date: 2021
  • (2020)Transaction-Based Core Reliability2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS47924.2020.00027(168-179)Online publication date: May-2020
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      Published In

      cover image ACM Conferences
      ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture
      June 2007
      542 pages
      ISBN:9781595937063
      DOI:10.1145/1250662
      • General Chair:
      • Dean Tullsen,
      • Program Chair:
      • Brad Calder
      • cover image ACM SIGARCH Computer Architecture News
        ACM SIGARCH Computer Architecture News  Volume 35, Issue 2
        May 2007
        527 pages
        ISSN:0163-5964
        DOI:10.1145/1273440
        Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 09 June 2007

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      Author Tags

      1. contention management
      2. hardware
      3. pathology
      4. performance
      5. transactional memory

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      Cited By

      View all
      • (2022)Metasystem Pathologies in Complex System GovernanceComplex System Governance10.1007/978-3-030-93852-9_9(241-282)Online publication date: 19-Apr-2022
      • (2021)DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional MemoryIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.3085210(1-1)Online publication date: 2021
      • (2020)Transaction-Based Core Reliability2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS47924.2020.00027(168-179)Online publication date: May-2020
      • (2020)PfTouch: Concurrent page-fault handling for Intel restricted transactional memoryJournal of Parallel and Distributed Computing10.1016/j.jpdc.2020.06.009145(111-123)Online publication date: Nov-2020
      • (2019)Simplifying Transactional Memory Support in C++ACM Transactions on Architecture and Code Optimization10.1145/332879616:3(1-24)Online publication date: 25-Jul-2019
      • (2019)Encapsulated open nesting for STMProceedings of the 24th Symposium on Principles and Practice of Parallel Programming10.1145/3293883.3295723(315-326)Online publication date: 16-Feb-2019
      • (2019)Applying Transactional Memory for Concurrency-Bug Failure Recovery in Production RunsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2018.287765630:5(990-1006)Online publication date: 1-May-2019
      • (2019)Optimizing Persistent Memory Transactions2019 28th International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT.2019.00025(219-231)Online publication date: Sep-2019
      • (2019)Forgive-TM: Supporting Lazy Conflict Detection In Eager Hardware Transactional Memory2019 28th International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT.2019.00023(192-204)Online publication date: Sep-2019
      • (2018)The Transactional Conflict ProblemProceedings of the 30th on Symposium on Parallelism in Algorithms and Architectures10.1145/3210377.3210406(383-392)Online publication date: 11-Jul-2018
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