Article

Making the fast case common and the uncommon case simple in unbounded transactional memory

Authors:

Colin Blundell,

E. Christopher Lewis,

Milo M. K. MartinAuthors Info & Claims

ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture

Pages 24 - 34

https://doi.org/10.1145/1250662.1250667

Published: 09 June 2007 Publication History

Abstract

Hardware transactional memory has great potential to simplify the creation ofcorrect and efficient multithreaded programs, allowing programmers to exploitmore effectively the soon-to-be-ubiquitous multi-core designs. Several recentproposals have extended the original bounded transactional memory to unboundedtransactional memory, a crucial step toward transactions becoming ageneral-purpose primitive. Unfortunately, supporting the concurrent executionof an unbounded number of unbounded transactions is challenging, and as aresult, many proposed implementations are complex.

This paper explores a different approach. First, we introduce thepermissions-only cache to extend the bound at which transactions overflow toallow the fast, bounded case to be used as frequently as possible. Second, wepropose OneTM to simplify the implementation of unbounded transactional memoryby bounding the concurrency of transactions that overflow the cache. Thesemechanisms work synergistically to provide a simple and fast unboundedtransactional memory system.

The permissions-only cache efficiently maintains the coherencepermissions-but not data-for blocks read or written transactionally thathave been evicted from the processor's caches. By holding coherencepermissions for these blocks, the regular cache coherence protocol can be usedto detect transactional conflicts using only a few bits of on-chip storage peroverflowed cache block.OneTM allows only one overflowed transaction at a time, relying on thepermissions-only cache to ensure that overflow is infrequent. We present twoimplementations. In OneTM-Serialized, an overflowed transaction simply stallsall other threads in the application.

In OneTM-Concurrent, non-overflowedtransactions and non-transactional code can execute concurrently with theoverflowed transaction, providing more concurrency while retaining OneTM's coresimplifying assumption.

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Cai ZBlackburn SBond MWang ZWrigstad T(2021)Understanding and utilizing hardware transactional memory capacityProceedings of the 2021 ACM SIGPLAN International Symposium on Memory Management10.1145/3459898.3463901(1-14)Online publication date: 22-Jun-2021
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Jeong JHong JMaeng SJung CKwon Y(2020)Unbounded Hardware Transactional Memory for a Hybrid DRAM/NVM Memory System2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO50266.2020.00051(525-538)Online publication date: Oct-2020
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Quislant RGutierrez EZapata EPlata O(2019)Improving hardware transactional memory parallelization of computational geometry algorithms using privatizing transactionsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2019.04.018Online publication date: May-2019
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Index Terms

Making the fast case common and the uncommon case simple in unbounded transactional memory
1. Computer systems organization
  1. Architectures
    1. Parallel architectures

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Published In

cover image ACM Conferences

ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture

June 2007

542 pages

ISBN:9781595937063

DOI:10.1145/1250662

General Chair:
Dean Tullsen
University of California, San Diego
,
Program Chair:
Brad Calder
Microsoft & University of California, San Diego

ACM SIGARCH Computer Architecture News Volume 35, Issue 2
May 2007
527 pages
ISSN:0163-5964
DOI:10.1145/1273440
Issue’s Table of Contents

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 09 June 2007

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Cited By

Cai ZBlackburn SBond MWang ZWrigstad T(2021)Understanding and utilizing hardware transactional memory capacityProceedings of the 2021 ACM SIGPLAN International Symposium on Memory Management10.1145/3459898.3463901(1-14)Online publication date: 22-Jun-2021
https://dl.acm.org/doi/10.1145/3459898.3463901
Jeong JHong JMaeng SJung CKwon Y(2020)Unbounded Hardware Transactional Memory for a Hybrid DRAM/NVM Memory System2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO50266.2020.00051(525-538)Online publication date: Oct-2020
https://doi.org/10.1109/MICRO50266.2020.00051
Quislant RGutierrez EZapata EPlata O(2019)Improving hardware transactional memory parallelization of computational geometry algorithms using privatizing transactionsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2019.04.018Online publication date: May-2019
https://doi.org/10.1016/j.jpdc.2019.04.018
Park SHughes CPrvulovic MEvripidou SStenström PO'Boyle M(2018)Transactional pre-abort handlers in hardware transactional memoryProceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques10.1145/3243176.3243186(1-11)Online publication date: 1-Nov-2018
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Dice DHerlihy MKogan A(2018)Improving Parallelism in Hardware Transactional MemoryACM Transactions on Architecture and Code Optimization10.1145/317796215:1(1-24)Online publication date: 22-Mar-2018
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Sengupta ACao MBond MKulkarni MReddi VSmith ATang L(2017)Legato: end-to-end bounded region serializability using commodity hardware transactional memoryProceedings of the 2017 International Symposium on Code Generation and Optimization10.5555/3049832.3049834(1-13)Online publication date: 4-Feb-2017
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