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A model for estimating trace-sample miss ratios

Published: 02 April 1991 Publication History

Abstract

Unknown references, also known as cold-start misses, arise during trace-driven simulation of uniprocessor caches because of the unknown initial conditions. Accurately estimating the miss ratio of unknown references, denoted by μ, is particularly important when simulating large caches with short trace samples, since many references may be unknown.In this paper we make three contributions regarding μ. First, we provide empirical evidence that μ is much larger than the overall miss ratio (e.g., 0.40 vs. 0.02). Prior work suggests that they should be the same. Second, we develop a model that explains our empirical results for long trace samples. In our model, each block frame is either live, if its next reference will hit, or dead, if its next reference will miss. We model each block frame as an alternating renewal process, and use the renewal-reward theorem to show that μ is simply the fraction of time block frames are dead. Finally, we extend the model to handle short trace samples and use it to develop several estimators of μ. Trace-driven simulation results show these estimators lead to better estimates of overall miss ratios than do previous methods.

References

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Peter J. Bickel and Kjell A. Doksum. Mathematical Statistics. Holden-Day, Inc., San Francisco, 1977.
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Malcom C. Easton and Ronald Fagin. Cold-start vs. warm-start miss ratios. Communications of the A CM, 21(10), October 1978.
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  • (2019)Infection-Based Dead Page Prediction in Hybrid Memory ArchitectureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.292266027:10(2401-2412)Online publication date: Oct-2019
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cover image ACM Conferences
SIGMETRICS '91: Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems
April 1991
228 pages
ISBN:0897913922
DOI:10.1145/107971
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 02 April 1991

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Cited By

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  • (2019)Infection-Based Dead Page Prediction in Hybrid Memory ArchitectureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.292266027:10(2401-2412)Online publication date: Oct-2019
  • (2019)Epsim: A Scalable and Parallel Marssx86 Simulator With Exploiting Epoch-Based ExecutionIEEE Access10.1109/ACCESS.2018.28866307(4782-4794)Online publication date: 2019
  • (2018)Global Dead-Block Management for Task-Parallel ProgramsACM Transactions on Architecture and Code Optimization10.1145/323433715:3(1-25)Online publication date: 4-Sep-2018
  • (2017)Computational video editing for dialogue-driven scenesACM Transactions on Graphics10.1145/3072959.307365336:4(1-14)Online publication date: 20-Jul-2017
  • (2017)Runtime-Assisted Global Cache Management for Task-Based Parallel ProgramsIEEE Computer Architecture Letters10.1109/LCA.2016.260659316:2(145-148)Online publication date: 1-Jul-2017
  • (2016)Efficient TLB-Based Detection of Private Pages in Chip MultiprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2015.241213927:3(748-761)Online publication date: 1-Mar-2016
  • (2016)RADAR: Runtime-assisted dead region management for last-level caches2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446101(644-656)Online publication date: Mar-2016
  • (2015)The Effects of Granularity and Adaptivity on Private/Shared Classification for CoherenceACM Transactions on Architecture and Code Optimization10.1145/279030112:3(1-21)Online publication date: 31-Aug-2015
  • (2014)A Primer on Hardware PrefetchingSynthesis Lectures on Computer Architecture10.2200/S00581ED1V01Y201405CAC0289:1(1-67)Online publication date: 31-May-2014
  • (2014)Reducing cache leakage energy for hybrid SPM-cache architecturesProceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.1145/2656106.2656124(1-9)Online publication date: 12-Oct-2014
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