Article

Automatic generation of customized discrete fourier transform IPs

Authors:

Grace Nordin,

Peter A. Milder,

James C. Hoe,

Markus PüschelAuthors Info & Claims

DAC '05: Proceedings of the 42nd annual Design Automation Conference

Pages 471 - 474

https://doi.org/10.1145/1065579.1065703

Published: 13 June 2005 Publication History

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Abstract

This paper presents a parameterized soft core generator for the discrete Fourier transform (DFT). Reusable IPs of digital signal processing (DSP) kernels are important time-saving resources in DSP hardware development. Unfortunately, reusable IPs, however optimized, can introduce inefficiencies because they cannot fit the exact requirements of every application context. Given the well-understood and regular computation in DSP kernels, an automatic tool can generate high-quality ready-to-use IPs customized to user-specified cost/performance tradeoffs (beyond basic parameters such as input size and data format). The paper shows that the generated DFT cores can match closely the performance and cost of DFT cores from the Xilinx LogiCore library. Furthermore, the generator can yield DFT cores over a range of different performance/ cost tradeoff points that are not available from the library.

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Xilinx, Inc. Xilinx LogiCore: Fast Fourier Transform v3.1, November 2004.

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Deiana ATran NAgar JBlott MDi Guglielmo GDuarte JHarris PHauck SLiu MNeubauer MNgadiuba JOgrenci-Memik SPierini MAarrestad TBähr SBecker JBerthold ABonventre RMüller Bravo TDiefenthaler MDong ZFritzsche NGholami AGovorkova EGuo DHazelwood KHerwig CKhan BKim SKlijnsma TLiu YLo KNguyen TPezzullo GRasoulinezhad SRivera RScholberg KSelig JSen SStrukov DTang WThais SUnger KVilalta Rvon Krosigk BWang SWarburton T(2022)Applications and Techniques for Fast Machine Learning in ScienceFrontiers in Big Data10.3389/fdata.2022.7874215Online publication date: 12-Apr-2022
https://doi.org/10.3389/fdata.2022.787421
Mirfarshbafan STaner SStuder C(2021)SMUL-FFT: A Streaming Multiplierless Fast Fourier TransformIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2021.306423868:5(1715-1719)Online publication date: May-2021
https://doi.org/10.1109/TCSII.2021.3064238
Ji CShen YZhang ZYou XZhang C(2020)Autogeneration of Pipelined Belief Propagation Polar DecodersIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.2983975(1-14)Online publication date: 2020
https://doi.org/10.1109/TVLSI.2020.2983975
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Index Terms

Automatic generation of customized discrete fourier transform IPs
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

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Information & Contributors

Information

Published In

DAC '05: Proceedings of the 42nd annual Design Automation Conference

June 2005

984 pages

ISBN:1595930582

DOI:10.1145/1065579

General Chair:
William H. Joyner
IBM Corp./SRC
,
Program Chairs:
Grant E. Martin
Tensilica, Inc.
,
Andrew B. Kahng
University of California at San Diego, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2005

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DAC05: The 42nd Annual Design Automation Conference 2005

June 13 - 17, 2005

California, Anaheim, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Deiana ATran NAgar JBlott MDi Guglielmo GDuarte JHarris PHauck SLiu MNeubauer MNgadiuba JOgrenci-Memik SPierini MAarrestad TBähr SBecker JBerthold ABonventre RMüller Bravo TDiefenthaler MDong ZFritzsche NGholami AGovorkova EGuo DHazelwood KHerwig CKhan BKim SKlijnsma TLiu YLo KNguyen TPezzullo GRasoulinezhad SRivera RScholberg KSelig JSen SStrukov DTang WThais SUnger KVilalta Rvon Krosigk BWang SWarburton T(2022)Applications and Techniques for Fast Machine Learning in ScienceFrontiers in Big Data10.3389/fdata.2022.7874215Online publication date: 12-Apr-2022
https://doi.org/10.3389/fdata.2022.787421
Mirfarshbafan STaner SStuder C(2021)SMUL-FFT: A Streaming Multiplierless Fast Fourier TransformIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2021.306423868:5(1715-1719)Online publication date: May-2021
https://doi.org/10.1109/TCSII.2021.3064238
Ji CShen YZhang ZYou XZhang C(2020)Autogeneration of Pipelined Belief Propagation Polar DecodersIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.2983975(1-14)Online publication date: 2020
https://doi.org/10.1109/TVLSI.2020.2983975
Zhong ZGross WZhang ZYou XZhang C(2020)Polar Compiler: Auto-Generator of Hardware Architectures for Polar EncodersIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.296932567:6(2091-2102)Online publication date: Jun-2020
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Serre FPüschel M(2019)DSL-Based Hardware Generation with ScalaACM Transactions on Reconfigurable Technology and Systems10.1145/335975413:1(1-23)Online publication date: 19-Dec-2019
https://dl.acm.org/doi/10.1145/3359754
Serre FPuschel M(2019)In Search of the Optimal Walsh-hadamard Transform for Streamed Parallel ProcessingICASSP 2019 - 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)10.1109/ICASSP.2019.8682213(1532-1536)Online publication date: May-2019
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Serre FPuschel M(2019)DSL-Based Modular IP Core Generators: Example FFT and Related Structures2019 IEEE 26th Symposium on Computer Arithmetic (ARITH)10.1109/ARITH.2019.00043(190-191)Online publication date: Jun-2019
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Serre FPüschel MAnderson JBazargan K(2018)Memory-Efficient Fast Fourier Transform on Streaming Data by Fusing PermutationsProceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3174243.3174263(219-228)Online publication date: 15-Feb-2018
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Franchetti FLow TPopovici DVeras RSpampinato DJohnson JPuschel MHoe JMoura J(2018)SPIRAL: Extreme Performance PortabilityProceedings of the IEEE10.1109/JPROC.2018.2873289106:11(1935-1968)Online publication date: Nov-2018
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