Article

A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only)

Authors:

H. Hassan,

M. Anis,

M. ElmasryAuthors Info & Claims

FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

Page 267

https://doi.org/10.1145/1046192.1046237

Published: 20 February 2005 Publication History

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Abstract

FPGAs are witnessing a big increase in their applications, especially with the introduction of state-of-the-art FPGAs using nanometer technologies. This has been accompanied with a big increase in power dissipation in FPGAs, which forms a road block to the integration of FPGAs in several hand-held applications. Motivated by the increase in the percentage of leakage power dissipation to the total power dissipation in modern technologies, this work presents a complete CAD flow to mitigate leakage power dissipation in FPGAs. The algorithm is based on a FPGA architecture that employs multi-threshold CMOS technology. The flow is based on the VPR flow and it aims to pack and place logic blocks that exhibit similar idleness close to each other so that they can be turned off during their idle time. The flow is tested with a CMOS 0.13 m dual-vth technology and achieved an average power saving of 22%.

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Hironaka KAmano H(2011)Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual VthProceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs10.1109/ReConFig.2011.70(404-409)Online publication date: 30-Nov-2011
https://dl.acm.org/doi/10.1109/ReConFig.2011.70
Hirai KKato MSaito YAmano H(2009)Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells2009 International Conference on Field-Programmable Technology10.1109/FPT.2009.5377641(104-111)Online publication date: Dec-2009
https://doi.org/10.1109/FPT.2009.5377641

A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only)
1. Hardware

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Published In

FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

February 2005

288 pages

ISBN:1595930299

DOI:10.1145/1046192

General Chair:
Herman Schmit
Tabula
,
Program Chair:
Steve Wilton
University of British Columbia

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 20 February 2005

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FPGA05

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FPGA05: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2005

February 20 - 22, 2005

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

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Hironaka KAmano H(2011)Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual VthProceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs10.1109/ReConFig.2011.70(404-409)Online publication date: 30-Nov-2011
https://dl.acm.org/doi/10.1109/ReConFig.2011.70
Hirai KKato MSaito YAmano H(2009)Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells2009 International Conference on Field-Programmable Technology10.1109/FPT.2009.5377641(104-111)Online publication date: Dec-2009
https://doi.org/10.1109/FPT.2009.5377641

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