Article

The Stratix II logic and routing architecture

FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

Pages 14 - 20

Published: 20 February 2005 Publication History

Abstract

This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits containing a range of LUT sizes that arises in conventional synthesis flows. This provides a performance increase of 15% in the Stratix II architecture while reducing area by 2%. The ALM also includes a more powerful arithmetic structure that can perform two bits of arithmetic per ALM, and perform a sum of up to three inputs. The routing fabric adds a new set of fast inputs to the routing multiplexers for another 3% improvement in performance, while other improvements in routing efficiency cause another 6% reduction in area. These changes in combination with other circuit and architecture changes in Stratix II contribute 27% of an overall 51% performance improvement (including architecture and process improvement). The architecture changes reduce area by 10% in the same process, and by 50% after including process migration.

References

[1]

D. Lewis et al, "The Stratix™ Logic and Routing Architecture", Proc FPGA-02, pp 12--20.

Digital Library

Google Scholar

[2]

Elias Ahmed and Jonathan Rose, "The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density", Proc FPGA-00, pp 3--12.

Digital Library

Google Scholar

[3]

V. Betz, J. Rose, and A. Marquardt, "Architecture and CAD for Deep-Submicron FPGAs", Kluwer Academic Publishers, 1999.

Digital Library

Google Scholar

[4]

M. Hutton et al, "Interconnect Enhancements for a High-Speed PLD Architecture", Proc FPGA-00, pp 3--10.

Digital Library

Google Scholar

[5]

R. Cliff et al, "A Next Generation Architecture Optimized for High Density System Level Integration", Proc. CICC-99, pp 175--178.

Google Scholar

[6]

M. Hutton, K. Adibsamii, and A. Leaver, "Timing Driven Placement for Hierarchical Programmable Logic Devices", Proc. FPGA-01, pp 3--11.

Digital Library

Google Scholar

[7]

K. Veenstra et al, "Optimizations for a Highly Cost-Efficient Programmable Logic Architecture", Proc FPGA-98, pp 20--24.

Digital Library

Google Scholar

[8]

V. Betz and J. Rose, "FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density", Proc FPGA-99, pp 59--68.

Digital Library

Google Scholar

[9]

V. Betz and J. Rose, "Effect of the Prefabricated Routing Track Distribution on FPGA Area-Efficiency", IEEE Trans. VLSI, Sept 1998, pp 445--456.

Digital Library

Google Scholar

[10]

V. Betz and J. Rose, "Automatic Generation of FPGA Routing Architectures from High-Level Descriptions", Proc. FPGA-00, pp 175--184.

Digital Library

Google Scholar

[11]

D. Cherepacha and D. Lewis, "A Datapath Oriented Architecture for FPGAs", Proc. FPGA-94.

Google Scholar

[12]

M. Hutton, et al, "Improving FPGA Performance and Area Using an Adaptive Logic Module", in Proc. Int'l Conference on Field Programmable logic and its applications Proc. FPL-04, pp. 135--144, 2004.

Google Scholar

[13]

E. Ahmed, "The Effect of Logic Block Granularity on Deep-Submicron FPGA Performance and Density", MASc Thesis, University of Toronto, 2001.

Google Scholar

Cited By

View all

Barajas GGreene JLi FTandon J(2023)Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models2023 24th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED57927.2023.10129290(1-6)Online publication date: 5-Apr-2023
https://doi.org/10.1109/ISQED57927.2023.10129290
Shi KZhou HWang L(2023)Explore the Feedback Interconnects in Intra-Cluster Routing for FPGAs2023 International Conference on Field Programmable Technology (ICFPT)10.1109/ICFPT59805.2023.00034(250-253)Online publication date: 12-Dec-2023
https://doi.org/10.1109/ICFPT59805.2023.00034
Mohaghegh ABetz V(2023)Tear Down The Wall: Unified and Efficient Intra-and Inter-Cluster Routing for FPGAs2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL60245.2023.00026(130-136)Online publication date: 4-Sep-2023
https://doi.org/10.1109/FPL60245.2023.00026
Show More Cited By

Index Terms

The Stratix II logic and routing architecture
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

Recommendations

The Stratix™ 10 Highly Pipelined FPGA Architecture
FPGA '16: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

This paper describes architectural enhancements in the Altera Stratix? 10 HyperFlex? FPGA architecture, fabricated in the Intel 14nm FinFET process. Stratix 10 includes ubiquitous flip-flops in the routing to enable a high degree of pipelining. In ...
Architectural enhancements in Stratix V™
FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

This paper describes architectural enhancements in the Altera Stratix-V" FPGA architecture, built on a 28nm TSMC process, together with the data supporting those choices. Among the key features are time borrowing flip-flops, a doubling of the number of ...
An architecture for a DSP field-programmable gate array

This paper describes an application specific architecture for field-programmable gate arrays (FPGAs). Emphasis is placed on the logic module architecture and channel segmentation for the FPGAs targeted for application areas related to digital signal ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

February 2005

288 pages

ISBN:1595930299

DOI:10.1145/1046192

General Chair:
Herman Schmit
Tabula
,
Program Chair:
Steve Wilton
University of British Columbia

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 20 February 2005

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

FPGA05

Sponsor:

FPGA05: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2005

February 20 - 22, 2005

California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

157
Total Citations
View Citations
2,006
Total Downloads

Downloads (Last 12 months)81
Downloads (Last 6 weeks)1

Reflects downloads up to 22 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Barajas GGreene JLi FTandon J(2023)Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models2023 24th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED57927.2023.10129290(1-6)Online publication date: 5-Apr-2023
https://doi.org/10.1109/ISQED57927.2023.10129290
Shi KZhou HWang L(2023)Explore the Feedback Interconnects in Intra-Cluster Routing for FPGAs2023 International Conference on Field Programmable Technology (ICFPT)10.1109/ICFPT59805.2023.00034(250-253)Online publication date: 12-Dec-2023
https://doi.org/10.1109/ICFPT59805.2023.00034
Mohaghegh ABetz V(2023)Tear Down The Wall: Unified and Efficient Intra-and Inter-Cluster Routing for FPGAs2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL60245.2023.00026(130-136)Online publication date: 4-Sep-2023
https://doi.org/10.1109/FPL60245.2023.00026
Khoozani KDehkordi ABetz V(2023)Titan 2.0: Enabling Open-Source CAD Evaluation with a Modern Architecture Capture2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL60245.2023.00016(57-64)Online publication date: 4-Sep-2023
https://doi.org/10.1109/FPL60245.2023.00016
Boutros ABetz V(2023)Field-Programmable Gate Array ArchitectureHandbook of Computer Architecture10.1007/978-981-15-6401-7_49-1(1-47)Online publication date: 7-Jan-2023
https://doi.org/10.1007/978-981-15-6401-7_49-1
Zamiri Azar KMardani Kamali HFarahmandi FTehranipoor MZamiri Azar KMardani Kamali HFarahmandi FTehranipoor M(2023)Fundamentals of Logic LockingUnderstanding Logic Locking10.1007/978-3-031-37989-5_5(89-107)Online publication date: 26-Jun-2023
https://doi.org/10.1007/978-3-031-37989-5_5
Shi KZhou XZhou HWang L(2022)An Optimized GIB Routing Architecture with Bent Wires for FPGAACM Transactions on Reconfigurable Technology and Systems10.1145/351959916:1(1-28)Online publication date: 22-Dec-2022
https://dl.acm.org/doi/10.1145/3519599
Petersen MNikolić SStojilović MShannon LAdler M(2021)NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAsThe 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3431920.3439285(11-22)Online publication date: 17-Feb-2021
https://dl.acm.org/doi/10.1145/3431920.3439285
Boutros ABetz V(2021)FPGA Architecture: Principles and ProgressionIEEE Circuits and Systems Magazine10.1109/MCAS.2021.307160721:2(4-29)Online publication date: Oct-2022
https://doi.org/10.1109/MCAS.2021.3071607
Chromczak JWheeler MChiasson CHow DLanghammer MVanderhoek TZgheib GGanusov INeuendorffer SShannon L(2020)Architectural Enhancements in Intel® Agilex™ FPGAsProceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3373087.3375308(140-149)Online publication date: 23-Feb-2020
https://dl.acm.org/doi/10.1145/3373087.3375308
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

The Stratix™ 10 Highly Pipelined FPGA Architecture

Architectural enhancements in Stratix V™

An architecture for a DSP field-programmable gate array