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B*-Trees: a new representation for non-slicing floorplans

Published: 01 June 2000 Publication History

Abstract

We present in this paper an efficient, flexible, and effective data structure, B*-trees for non-slicing floorplans. B*-trees are based on ordered binary trees and the admissible placement presented in [1]. Inheriting from the nice properties of ordered binary trees, B*-trees are very easy for implementation and can perform the respective primitive tree, operations search, insertion, and deletion in only O(1), O(1), and O(n) times while existing representations for non-slicing floorplans need at least O(n) time for each of these operations, where n is the number of modules. The correspondence between an admissible placement and its induced B*-tree is 1-to-1 (i.e., no redundancy); further, the transformation between them takes only linear time. Unlike other representations for non-slicing floorplans that need to construct constraint graphs for cost evaluation, in particular, the evaluation can be performed on B*-trees and their corresponding placements directly and incrementally. We further show the flexibility of B*-trees by exploring how to handle rotated, pre-placed, soft, and rectilinear modules. Experimental results on MCNC benchmarks show that the B*-tree representation runs about 4.5 times faster, consumes about 60% less memory, and results in smaller silicon area than the O-tree one [1]. We also develop a B*-tree based simulated annealing scheme for floorplan design; the scheme achieves near optimum area utilization even for rectilinear modules.

References

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R-N. Guo, C.-K. Cheng, and T. Yoshimura, "An O-Tree Representation of Non- Slicing Floorplan and Its Applications,"P1vc. DAC, pp. 268-273, 1999.
[2]
M. Kang and W. Dai., "General Floorplanning with L-shaped, T-shaped and Soft Blocks Based on Bounded Slicing Grid Structure," Proc. ASP-DAC, 1997.
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cover image ACM Conferences
DAC '00: Proceedings of the 37th Annual Design Automation Conference
June 2000
819 pages
ISBN:1581131879
DOI:10.1145/337292
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 2000

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  • (2024)Reinforcement learning within tree search for fast macro placementProceedings of the 41st International Conference on Machine Learning10.5555/3692070.3692687(15402-15417)Online publication date: 21-Jul-2024
  • (2024)A Deep Reinforcement Learning Floorplanning Algorithm Based on Sequence PairsApplied Sciences10.3390/app1407290514:7(2905)Online publication date: 29-Mar-2024
  • (2024)Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience ReplayACM Transactions on Design Automation of Electronic Systems10.1145/365345329:3(1-17)Online publication date: 3-May-2024
  • (2024)Floorplet: Performance-Aware Floorplan Framework for Chiplet IntegrationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334730243:6(1638-1649)Online publication date: Jun-2024
  • (2024) Hier-RTLMP : A Hierarchical Automatic Macro Placer for Large-Scale Complex IP Blocks IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334628443:5(1552-1565)Online publication date: May-2024
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  • (2024)Automatic Multi-Constraint Placement of Printed Circuit Board2024 13th International Conference on Communications, Circuits and Systems (ICCCAS)10.1109/ICCCAS62034.2024.10652855(1-6)Online publication date: 10-May-2024
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