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Prediction and bounds on shared cache demand from memory access interleaving

Published: 18 June 2018 Publication History

Abstract

Cache in multicore machines is often shared, and the cache performance depends on how memory accesses belonging to different programs interleave with one another. The full range of performance possibilities includes all possible interleavings, which are too numerous to be studied by experiments for any mix of non-trivial programs.
This paper presents a theory to characterize the effect of memory access interleaving due to parallel execution of non-data-sharing programs. The theory uses an established metric called the footprint (which can be used to calculate miss ratios in fully-associative LRU caches) to measure cache demand, and considers the full range of interleaving possibilities. The paper proves a lower bound for footprints of interleaved traces, and then formulates an upper bound in terms of the footprints of the constituent traces. It also shows the correctness of footprint composition used in a number of existing techniques, and places precise bounds on its accuracy.

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    Published In

    cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 53, Issue 5
    ISMM '18
    May 2018
    119 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/3299706
    Issue’s Table of Contents
    • cover image ACM Conferences
      ISMM 2018: Proceedings of the 2018 ACM SIGPLAN International Symposium on Memory Management
      June 2018
      119 pages
      ISBN:9781450358019
      DOI:10.1145/3210563
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 18 June 2018
    Published in SIGPLAN Volume 53, Issue 5

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    Author Tags

    1. Footprint
    2. Multicore
    3. Parallel Processing
    4. Performance Prediction
    5. Shared Cache

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