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Architectural support for the management of tightly-coupled fine-grain goals in flat concurrent Prolog

Published: 01 May 1990 Publication History

Abstract

We propose architectural support for goal management as part of a special-purpose processor architecture for the efficient execution of Flat Concurrent Prolog. Goal management operations: halt, spawn, suspend and commit are decoupled from goal reduction, and overlapped in the Goal Management Unit. Their efficient execution is enabled using a Goal Cache. We evaluate the performance of the goal management support using an analytic performance model and program parameters characteristic of the System's Development Workload. Most goal management operations are completely overlapped, resulting in a speedup of 2. Higher speedups are obtained for workloads that exhibit greater goal management complexity.

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Cited By

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  • (2002)Logic Programming Languages for the InternetComputational Logic: Logic Programming and Beyond, Essays in Honour of Robert A. Kowalski, Part I10.5555/646001.675774(66-104)Online publication date: 1-Jan-2002
  • (2005)Sequentialization of parallel logic programs with mode analysisLogic Programming and Automated Reasoning10.1007/3-540-56944-8_54(205-216)Online publication date: 7-Jun-2005

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  1. Architectural support for the management of tightly-coupled fine-grain goals in flat concurrent Prolog

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    Published In

    cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 18, Issue 2SI
    Special Issue: Proceedings of the 17th annual international symposium on Computer Architecture
    June 1990
    356 pages
    ISSN:0163-5964
    DOI:10.1145/325096
    Issue’s Table of Contents

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 01 May 1990
    Published in SIGARCH Volume 18, Issue 2SI

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    • (2002)Logic Programming Languages for the InternetComputational Logic: Logic Programming and Beyond, Essays in Honour of Robert A. Kowalski, Part I10.5555/646001.675774(66-104)Online publication date: 1-Jan-2002
    • (2005)Sequentialization of parallel logic programs with mode analysisLogic Programming and Automated Reasoning10.1007/3-540-56944-8_54(205-216)Online publication date: 7-Jun-2005

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