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A methodology and design environment for DSP ASIC fixed point refinement

Authors:

R. Cmar,

L. Rijnders,

P. Schaumont,

S. Vernalde,

I. BolsensAuthors Info & Claims

DATE '99: Proceedings of the conference on Design, automation and test in Europe

Pages 56 - es

https://doi.org/10.1145/307418.307503

Published: 01 January 1999 Publication History

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References

[1]

{1} W. Sung, K. Kum "Simulation-Based Word-Length Optimization Method for Fixed-Point Digital Signal Processing Systems", IEEE Transactions on Signal Processing, vol.43, pp. 3087-3090, Dec.1995.

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{2} S. Kim, K. Kum, W. Sung, "Fixed-Point Optimization Utility for C and C++ Based Digital Signal Processing Programs", Workshop on VLSI and Signal Processing '95, Osaka, pp. 197-206, Nov. 1995.

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{3} M. Willems, V. Bursgens, H. Keding, T. Grotker, H. Meyr, "System Level Fixed-Point Design Based on an Interpolative Approach", Proc. of the DAC, Anaheim, 1997.

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[4]

{4} Frontier Design, http://www.frontierd.com/artlibrary.htm

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[5]

{5} P. Schaumont, S. Vernalde, L. Rijnders, M. Engels, I. Bolsens, "A Programming Environment for the Design of Complex High Speed ASICs", Proc. of the DAC, Anaheim, 1997.

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TSUKADA MMATSUTANI H(2022)An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital CircuitIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2021VLP0017E105.A:3(437-447)Online publication date: 1-Mar-2022
https://doi.org/10.1587/transfun.2021VLP0017
Caffarena G(2022)Wordlength Optimization of Fixed-Point AlgorithmsApproximate Computing Techniques10.1007/978-3-030-94705-7_9(261-284)Online publication date: 3-Jan-2022
https://doi.org/10.1007/978-3-030-94705-7_9
Voss NKwaadgras BMencer OLuk WGaydadjiev G(2021)On Predictable Reconfigurable System DesignACM Transactions on Architecture and Code Optimization10.1145/343699518:2(1-28)Online publication date: 9-Feb-2021
https://dl.acm.org/doi/10.1145/3436995
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A methodology and design environment for DSP ASIC fixed point refinement
1. Hardware

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Published In

DATE '99: Proceedings of the conference on Design, automation and test in Europe

January 1999

730 pages

ISBN:1581131216

DOI:10.1145/307418

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 1999

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DATE99: Design Automation and Test in Europe Conference and Exhibition 1999

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TSUKADA MMATSUTANI H(2022)An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital CircuitIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2021VLP0017E105.A:3(437-447)Online publication date: 1-Mar-2022
https://doi.org/10.1587/transfun.2021VLP0017
Caffarena G(2022)Wordlength Optimization of Fixed-Point AlgorithmsApproximate Computing Techniques10.1007/978-3-030-94705-7_9(261-284)Online publication date: 3-Jan-2022
https://doi.org/10.1007/978-3-030-94705-7_9
Voss NKwaadgras BMencer OLuk WGaydadjiev G(2021)On Predictable Reconfigurable System DesignACM Transactions on Architecture and Code Optimization10.1145/343699518:2(1-28)Online publication date: 9-Feb-2021
https://dl.acm.org/doi/10.1145/3436995
Martínez-García Mde Castro ASanchez AGarrido J(2021)Word length selection method for HIL power converter modelsInternational Journal of Electrical Power & Energy Systems10.1016/j.ijepes.2020.106721(106721)Online publication date: Feb-2021
https://doi.org/10.1016/j.ijepes.2020.106721
Hong TKang YChung J(2020)InSight: An FPGA-Based Neuromorphic Computing System for Deep Neural NetworksJournal of Low Power Electronics and Applications10.3390/jlpea1004003610:4(36)Online publication date: 30-Oct-2020
https://doi.org/10.3390/jlpea10040036
Blaiech ABen Khalifa KBoubaker MBedoui M(2018)LVQ neural network optimized implementation on FPGA devices with multiple-wordlength operations for real-time systemsNeural Computing and Applications10.1007/s00521-016-2465-729:2(509-528)Online publication date: 1-Jan-2018
https://dl.acm.org/doi/10.1007/s00521-016-2465-7
Faraji SSalari ASheikhaei S(2016)Fixed-point implementation of interpolation-based MMSE MIMO detector in joint transmission scenario for LTE-A wireless standardAEU - International Journal of Electronics and Communications10.1016/j.aeue.2016.09.00470:11(1506-1514)Online publication date: Nov-2016
https://doi.org/10.1016/j.aeue.2016.09.004
Nehmeh RMenard DNogues EBanciu AMichel TRocher R(2016)Fast Integer Word-length Optimization for Fixed-point SystemsJournal of Signal Processing Systems10.1007/s11265-015-0990-885:1(113-128)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1007/s11265-015-0990-8
Moussa SM. Abdel Razik ADahmane AD'Amours CHamam H(2016)Rapid prototyping of MIMO-OFDM based on parity bit selected and permutation spreadingInternational Journal of Numerical Modelling: Electronic Networks, Devices and Fields10.1002/jnm.205129:1(115-128)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1002/jnm.2051
Benkrid ABenkrid K(2013)A statistical framework to minimise and predict the range values of quantisation errors in fixed-point FIR filters architecturesDigital Signal Processing10.1016/j.dsp.2012.09.00823:1(453-469)Online publication date: 1-Jan-2013
https://dl.acm.org/doi/10.1016/j.dsp.2012.09.008
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Automatic Design of Area-Efficient Configurable ASIC Cores

Architectural synthesis of fixed-point DSP datapaths using FPGAs

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