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Power supply noise analysis methodology for deep-submicron VLSI chip design

Authors:

Howard H. Chen,

David D. LingAuthors Info & Claims

DAC '97: Proceedings of the 34th annual Design Automation Conference

Pages 638 - 643

https://doi.org/10.1145/266021.266307

Published: 13 June 1997 Publication History

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Abstract

This paper describes a new design methodology to analyzethe on-chip power supply noise for high-performance microprocessors.Based on an integrated package-level andchip-level power bus model, and a simulated switching circuitmodel for each functional block, this methodology offersthe most complete and accurate analysis of Vdd distributionfor the entire chip. The analysis results not only providedesigners with the inductive ΔI noise and the resistive IRdrop data at the same time, but also allow designers to easilyidentify the hot spots on the chip and ΔV across the chip.Global and local optimization such as buffer sizing, powerbus sizing, and on-chip decoupling capacitor placement canthen be conducted to maximize the circuit performance andminimize the noise.

References

[1]

H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, 1990.

Google Scholar

[2]

W. Bowhill et al., "A 300 MHz 64b quad-issue CMOS RISC microprocessor," in Proc. International Solid-State Circuits Conference, pp. 182-183, February 1995.

Crossref

Google Scholar

[3]

L. Miller, "Controlled collapse reflow chip joining," IBM Journal of Research and Development, vol. 13, no. 3, pp. 239-250, 1969.

Digital Library

Google Scholar

[4]

B. Rubin, "An electromagnetic approach for modeling high-performance computer packages," IBM Journal of Research and Development, vol. 34, pp. 585-600, July 1990.

Digital Library

Google Scholar

[5]

B. Davari et al., "A high performance 0.25urn CMOS technology," in Proc. International Electron Devices Meeting, pp. 56-59, December 1988.

Google Scholar

[6]

D. Dobberpuhl et al., "A 200-MHz 64-bit dual-issue CMOS microprocessor," IEEE Journal of Solid-State Circuits, pp. 1555-1567, November 1992.

Crossref

Google Scholar

[7]

J. Seliskar et al., "Voltage limitation of 0.5urn CMOS on thin SOI," in Proc. International Symposium on Siliconon-Insulator Technology and Devices, pp. 118-119, May 1992.

Google Scholar

[8]

A. Acovic et al., "Hot carrier reliability of fully depleted accumulation mode SOI MOSFETs," in Proc. IEEE International SO1 Conference, pp. 134-135, October 1992.

Google Scholar

[9]

F. Assaderaghi et al., "A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation," in Proc. International Electron Devices Meeting, pp. 809- 812, December 1994.

Google Scholar

Cited By

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Roy SMillican SAgrawal V(2024)A Survey and Recent Advances: Machine Intelligence in Electronic TestingJournal of Electronic Testing10.1007/s10836-024-06117-740:2(139-158)Online publication date: 15-Apr-2024
https://doi.org/10.1007/s10836-024-06117-7
Vaghasiya HJain ATripathi J(2022)A Radial Basis Function Network-Based Surrogate-Assisted Swarm Intelligence Approach for Fast Optimization of Power Delivery NetworksIEEE Transactions on Signal and Power Integrity10.1109/TSIPI.2022.32171091(140-149)Online publication date: 2022
https://doi.org/10.1109/TSIPI.2022.3217109
Bhattacharjee PRana PBhattacharyya BMajumder A(2022)Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged ICIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309943841:6(1704-1715)Online publication date: Jun-2022
https://doi.org/10.1109/TCAD.2021.3099438
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Index Terms

Power supply noise analysis methodology for deep-submicron VLSI chip design

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Information

Published In

DAC '97: Proceedings of the 34th annual Design Automation Conference

June 1997

788 pages

ISBN:0897919203

DOI:10.1145/266021

Chairmen:
Ellen J. Yoffa
IBM T. J. Watson Research Center, Yorktown Heights, NY
,
Giovanni De Micheli
Stanford Univ., Stanford, CA
,
Jan M. Rabaey
Univ. of California, Berkeley

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 1997

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DAC97

Sponsor:

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DAC97: The 34th Design Automation Conference

June 9 - 13, 1997

California, Anaheim, USA

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DAC '97 Paper Acceptance Rate 139 of 400 submissions, 35%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Roy SMillican SAgrawal V(2024)A Survey and Recent Advances: Machine Intelligence in Electronic TestingJournal of Electronic Testing10.1007/s10836-024-06117-740:2(139-158)Online publication date: 15-Apr-2024
https://doi.org/10.1007/s10836-024-06117-7
Vaghasiya HJain ATripathi J(2022)A Radial Basis Function Network-Based Surrogate-Assisted Swarm Intelligence Approach for Fast Optimization of Power Delivery NetworksIEEE Transactions on Signal and Power Integrity10.1109/TSIPI.2022.32171091(140-149)Online publication date: 2022
https://doi.org/10.1109/TSIPI.2022.3217109
Bhattacharjee PRana PBhattacharyya BMajumder A(2022)Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged ICIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309943841:6(1704-1715)Online publication date: Jun-2022
https://doi.org/10.1109/TCAD.2021.3099438
Xie ZLi HXu XHu JChen YXie Y(2020)Fast IR drop estimation with machine learningProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415763(1-8)Online publication date: 2-Nov-2020
https://dl.acm.org/doi/10.1145/3400302.3415763
Nawaf SHussein MSadeem SFaysal S(2018)Investigation of the Power Grid Accuracy by CMOS Transistor Network using Matlab/ SimulinkTikrit Journal of Engineering Sciences10.25130/tjes.25.3.0425:3(19-23)Online publication date: 1-Sep-2018
https://doi.org/10.25130/tjes.25.3.04
Sharma VTripathi JShrimali H(2018)A Quick Assessment of Nonlinearity in Power Delivery Networks2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)10.1109/EDAPS.2018.8680881(1-3)Online publication date: Dec-2018
https://doi.org/10.1109/EDAPS.2018.8680881
Zhao YYang JZhao WTodri-Sanial ACheng Y(2018)Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal ConstraintJournal of Computer Science and Technology10.1007/s11390-018-1868-633:5(966-983)Online publication date: 12-Sep-2018
https://doi.org/10.1007/s11390-018-1868-6
Liu YHan CLin SLi J(2017)PSN‐aware circuit test timing prediction using machine learningIET Computers & Digital Techniques10.1049/iet-cdt.2016.003211:2(60-67)Online publication date: 25-Jan-2017
https://doi.org/10.1049/iet-cdt.2016.0032
Todri-Sanial AKundu SGirard PBosio ADilillo LVirazel A(2014)Globally Constrained Locally Optimized 3-D Power Delivery NetworksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.228380022:10(2131-2144)Online publication date: Oct-2014
https://doi.org/10.1109/TVLSI.2013.2283800
OKUMOTO TYOSHIKAWA KNAGATA M(2013)Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated CircuitsIEICE Transactions on Electronics10.1587/transele.E96.C.538E96.C:4(538-545)Online publication date: 2013
https://doi.org/10.1587/transele.E96.C.538
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A Design Methodology for Efficient Application-Specific On-Chip Interconnects

Low-power network-on-chip for high-performance SoC design

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