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Leap scratchpads: automatic memory and cache management for reconfigurable logic

Authors:

Joel EmerAuthors Info & Claims

FPGA '11: Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays

Pages 25 - 28

https://doi.org/10.1145/1950413.1950421

Published: 27 February 2011 Publication History

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Abstract

Developers accelerating applications on FPGAs or other reconfigurable logic have nothing but raw memory devices in their standard toolkits. Each project typically includes tedious development of single-use memory management. Software developers expect a programming environment to include automatic memory management. Virtual memory provides the illusion of very large arrays and processor caches reduce access latency without explicit programmer instructions.

LEAP scratchpads for reconfigurable logic dynamically allocate and manage multiple, independent, memory arrays in a large backing store. Scratchpad accesses are cached automatically in multiple levels, ranging from shared on-board, RAM-based, set-associative caches to private caches stored in FPGA RAM blocks. In the LEAP framework, scratchpads share the same interface as on-die RAM blocks and are plug-in replacements. Additional libraries support heap management within a storage set. Like software developers, accelerator authors using scratchpads may focus more on core algorithms and less on memory management.

References

[1]

Arvind. Bluespec: A Language for Hardware Design, Simulation, Synthesis and Verification. In MEMOCODE '03: Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, page 249. IEEE Computer Society, 2003.

Digital Library

Google Scholar

[2]

Z. Budimlic, A. M. Chandramowlishwaran, K. Knobe, G. N. Lowney, V. Sarkar, and L. Treggiari. Declarative Aspects of Memory Management in the Concurrent Collections Parallel Programming Model. In DAMP '09: Proceedings of the 4th Workshop on Declarative Aspects of Multicore Programming, pages 47--58. ACM, 2008.

Digital Library

Google Scholar

[3]

N. Dave, M. C. Ng, M. Pellauer, and Arvind. A design ow based on modular refinement. In Formal Methods and Models for Codesign (MEMOCODE), 2010 8th IEEE/ACM International Conference on, pages 11--20, Jul. 2010.

Google Scholar

[4]

M. B. Gokhale, J. M. Stone, J. Arnold, and M. Kalinowski. Stream-Oriented FPGA Computing in the Streams-C High Level Language. In FCCM '00: Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, page 49. IEEE Computer Society, 2000.

Digital Library

Google Scholar

[5]

S. S. Huang, A. Hormati, D. F. Bacon, and R. Rabbah. Liquid Metal: Object-Oriented Programming Across the Hardware/Software Boundary. In ECOOP '08: Proceedings of the 22nd European conference on Object-Oriented Programming, pages 76--103. Springer-Verlag, 2008.

Digital Library

Google Scholar

[6]

W. W. Hwu and P. P. Chang. Achieving High Instruction Cache Performance with an Optimizing Compiler. SIGARCH Comput. Archit. News, 17(3):242--251, 1989.

Digital Library

Google Scholar

[7]

C.-K. Luk and T. C. Mowry. Cooperative Prefetching: Compiler and Hardware Support for Effective Instruction Prefetching in Modern Processors. In MICRO 31: Proceedings of the 31st Annual ACM/IEEE International Symposium on Microarchitecture, pages 182--194. IEEE Computer Society Press, 1998.

Digital Library

Google Scholar

[8]

W. A. Najjar, W. Böhm, B. A. Draper, J. Hammes, R. Rinker, J. R. Beveridge, M. Chawathe, and C. Ross. High-Level Language Abstraction for Reconfigurable Computing. Computer, 36(8):63--69, 2003.

Digital Library

Google Scholar

[9]

A. Parashar, M. Adler, K. Fleming, M. Pellauer, and J. Emer. LEAP: A Virtual Platform Architecture for FPGAs. In CARL '10: The 1st Workshop on the Intersections of Computer Architecture and Reconfigurable Logic, 2010.

Google Scholar

[10]

A. Parashar, M. Adler, M. Pellauer, and J. Emer. Hybrid CPU/FPGA Performance Models. In WARP '08: The 3rd Workshop on Architectural Research Prototyping, 2008.

Google Scholar

[11]

M. Pellauer, M. Adler, D. Chiou, and J. Emer. Soft Connections: Addressing the Hardware-Design Modularity Problem. In DAC '09: Proceedings of the 46th Annual Design Automation Conference, pages 276--281. ACM, 2009.

Digital Library

Google Scholar

[12]

J. Simsa and S. Singh. Designing Hardware with Dynamic Memory Abstraction. In FPGA '10: Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 69--72. ACM, 2010.

Digital Library

Google Scholar

[13]

Xilinx, Inc. UG363: Virtex-6 FPGA Memory Resources User Guide. 2010.

Google Scholar

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Index Terms

Leap scratchpads: automatic memory and cache management for reconfigurable logic
1. Computer systems organization

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Published In

FPGA '11: Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays

February 2011

300 pages

ISBN:9781450305549

DOI:10.1145/1950413

General Chair:
John Wawrzynek
University of California, Berkeley, USA
,
Program Chair:
Katherine Compton
University of Wisconsin-Madison, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 27 February 2011

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FPGA '11

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SIGDA

FPGA '11: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 27 - March 1, 2011

CA, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Brandner JMayer FPhilippsen M(2024)Multilayer Multipurpose Caches for OpenMP Target Regions on FPGAsAdvancing OpenMP for Future Accelerators10.1007/978-3-031-72567-8_6(79-93)Online publication date: 23-Sep-2024
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Xue ZWu YEmer JSze V(2023)Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer CapacityProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623793(1347-1363)Online publication date: 28-Oct-2023
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Trivedi ABrunella MBaumann ACrooks NSchwarzkopf M(2023)CPU-free Computing: A Vision with a BlueprintProceedings of the 19th Workshop on Hot Topics in Operating Systems10.1145/3593856.3595906(1-14)Online publication date: 22-Jun-2023
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