Article

Interconnect-power dissipation in a microprocessor

Authors:

Nir Magen,

Avinoam Kolodny,

Uri Weiser,

Nachum ShamirAuthors Info & Claims

SLIP '04: Proceedings of the 2004 international workshop on System level interconnect prediction

Pages 7 - 13

https://doi.org/10.1145/966747.966750

Published: 14 February 2004 Publication History

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Abstract

Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the-art high-performance microprocessor designed for power efficiency. The analysis showed that interconnect power is over 50% of the dynamic power. Over 90% of the interconnect power is consumed by only 10% of the interconnections. Relations of interconnect power to wire length distribution and hierarchy level of nets were examined. In light of the results, a router's algorithms were modified, to use larger wire spacing and minimal length routing for the high power consuming interconnects. The power-aware router algorithm was tested on synthesized blocks, demonstrating average saving of 14% in the dynamic power consumption without timing degradation or area increase. The results demonstrate the obtainable benefits of tuning physical design algorithms to save power.

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Cited By

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Musale TGanti AGogoi AManna K(2024)Low Power Network-on-Chip Architecture Design Technique2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC62099.2024.10767805(1-6)Online publication date: 6-Oct-2024
https://doi.org/10.1109/VLSI-SoC62099.2024.10767805
Omshi MFaghih Mirzaee RReza AMirzaei M(2024)Low-Power Bus Encoding by Ternary LWC and Quaternary Transition Signaling: From Initial Concept to Circuit DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.333727732:4(682-694)Online publication date: Apr-2024
https://doi.org/10.1109/TVLSI.2023.3337277
Huang PWang YZhao ZYue D(2024)CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor SizingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.332859232:1(137-149)Online publication date: Jan-2024
https://doi.org/10.1109/TVLSI.2023.3328592
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Index Terms

Interconnect-power dissipation in a microprocessor
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Integrated circuits

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Reviews

Reviewer: Parthasarathi Dasgupta

This paper discusses the important issue of power dissipation in the design of high-performance microprocessors. Its major focus is on dynamic power consumption due to the switching of capacitors, and on the role of the interconnect power in this. The authors performed interconnect power analysis on a state-of-the-art microprocessor, made up of 77 million transistors in 130nm technology. The analysis was based on a stochastic dynamic power estimation method. For the purpose of the analysis, the authors considered the signal interconnect lengths between the drivers and receivers, but did not include the global clock grid. However, the capacitances included all types of capacitive loads, including the diffusion capacitances of the drivers, capacitances of the metal wiring, and the gate load of the receivers. Repeater gate and diffusion capacitances were also added to the original net. Metal capacitances included cross-capacitances between the nets, with the unit miller coupling factor (MCF). The results of the analysis indicate that interconnect switching accounts for about half of the total dynamic power consumption. The net topologies were split into two parts, namely, local and global nets. The local net was typically observed to have 30 percent higher fan out, and about 80 percent smaller interconnect capacitance, compared to the global net. However, as observed in the paper, the interconnect power was divided almost equally between the local and the global nets, due to the larger number of local nets. Ninety percent of the dynamic power was consumed by ten percent of the nets, and power reduction for these nets thus appeared to be the most demanding. The authors end by suggesting some methods to implement power-aware routing. One vital suggestion was to reduce capacitances, possibly via interconnect length reduction, and via increased spacing between routing wires. As a possible extension of an existing industrial router, based on rip-up and reroute, some of the nets were classified as power-critical nets, and rip-up of these nets was of the lowest priority. Some potential future work is also discussed. Online Computing Reviews Service

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Published In

SLIP '04: Proceedings of the 2004 international workshop on System level interconnect prediction

February 2004

111 pages

ISBN:1581138180

DOI:10.1145/966747

General Chair:
Lou Scheffer
Cadence, USA
,
Program Chair:
Igor Markov
University of Michigan, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 14 February 2004

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February 14 - 15, 2004

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Overall Acceptance Rate 6 of 8 submissions, 75%

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https://doi.org/10.1109/VLSI-SoC62099.2024.10767805
Omshi MFaghih Mirzaee RReza AMirzaei M(2024)Low-Power Bus Encoding by Ternary LWC and Quaternary Transition Signaling: From Initial Concept to Circuit DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.333727732:4(682-694)Online publication date: Apr-2024
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Abstract

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Index Terms

Recommendations

Leveraging Unused Cache Block Words to Reduce Power in CMP Interconnect

Wire topology optimization for low power CMOS

Timing-aware power-optimal ordering of signals

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