Abstract
The effects of transient bit flips on the operation of processor based architectures is investigated through fault injection experiments performed in the hardware itself by means of the interruption mechanism. Such an approach is based on the execution, as the consequence of an interruption signal assertion, of pieces of code called CEU (Code Emulating Upsets), asynchronously downloaded in a suitable memory area. This paper focuses in the methodology followed to set-up CEU injection experiments on a digital architecture, illustrating it main steps by means of a studied case: the 80C51 microcontroller. Results obtained from automated fault injection sessions performed using the capabilities of a devoted test system, will point out the capabilities and limitations of the studied approach.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
F. Bezerra, D. Hardy, R. Velazco, and H. Ziade, “TILMICRO, A New SEU Latch-up Tester for Microprocessors Initial Results on 32-bit Floating Point DSPs,” RADECS: Radiation and Its Effects on Components and Systems, pp. 296-301, 1995.
J.H. Elder, J. Osborn, W.A. Kolasinsky, and R. Koga, “A Method for Characterizing Microprocessor's Vulnerability to SEU,” IEEE Trans.on Nuclear Science, vol. 35, no. 6, pp. 1679-1681, Dec. 1988.
T. Ma and P. Dressendorfer, Ionizing Radiation Effects in MOS Devices and Circuits, Wiley Eds., New York, 1989.
E. Normand, “Single-Event Effects in Avionics,” IEEE Trans. on Nuclear Science, vol. 43, no. 2, pp. 461-474, April 1966.
S. Rezgui, “Etude d'une Méthode de Prédiction du Taux d'erreur d'architectures Digitales Exposées Aux Radiations,” Ph.D. Thesis of the Institut National Polytechnique de Grenoble France, presented in INPG, 30 March 2001.
S. Rezgui and R. Velazco, “Ground Testing of Architectures including Digital Signal Processors,” in Proc. of DSP Deutschland Mess & Kongress, 10-12 October 2000, Munich, Germany.
R. Velazco, Ph. Cheynet, A. Bofill, and R. Ecoffet, “THESIC: A Testbed Suitable for the Qualification of Integrated Circuits Devoted to Operate in Harsh Environment, in IEEE European Test Workshop (ETW' 98), Sitges, Espagne, May 1998, pp. 89-90.
R. Velazco, S. Karoui, T. Chapuis, D. Benezech, and L.H. Rosier, “Heavy Ion Tests for the 68020 Microprocessor and the 68882 Coprocessor,” IEEE Trans. on Nuclear Science, vol. 39, no. 3, Dec. 1992.
R. Velazco, S. Rezgui, and R. Ecoffet, “Predicting Error Rates for Microprocessor Based Digital Architectures by C.E.U. (Code Emulated Upsets) injection,” IEEE Transactions on Nuclear Science, vol. 47, no. 6, pp. 2405-2411, Dec. 2000.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Velazco, R., Rezgui, S. & Ziade, H. Assessing the Soft Error Rate of Digital Architectures Devoted to Operate in Radiation Environment: A Case Studied. Journal of Electronic Testing 19, 83–90 (2003). https://doi.org/10.1023/A:1021900130241
Issue Date:
DOI: https://doi.org/10.1023/A:1021900130241