Abstract
In the context of analog BIST for ADC, this paper presents two structures for the internal generation of a linear signal used with the histogram-based test technique. All of these structures use wide-swing current mirrors and an original adaptive system to make the generators less sensitive to process variations. The first structure allows us to generate high quality ramp signal. In a second step, a very high accuracy triangle-wave signal generator is presented in order to improve the equivalent linearity of the generated analog test signal.
Similar content being viewed by others
References
K. Arabi and B. Kaminska, “Oscillation Built-In Self-Test (OBIST) Scheme for Functional and Structural Testing of Analog and Mixed-Signal Integrated Circuits,” in Proc. International Test Conference, 1997, pp. 786-795.
F. Azaïs, S. Bernard, Y. Bertrand, X. Michel, and M. Renovell, “A Low-Cost Adaptive Ramp Generator for Analog BIST Applications,” in Proc. VLSI Test Symposium, 2001.
F. Azaïs, S. Bernard, Y. Bertrand, and M. Renovell, “Towards an ADC BIST Scheme using the Histogram Test Technique,” in Proc. European Test Workshop, 2000, pp. 129-134.
S. Bernard, F. Azaïs, Y. Bertrand, and M. Renovell, “Efficient On-Chip Generator for Linear Histogram BIST of ADCs,” in Proc. International Mixed-Signal Testing Workshop, 2001.
R. de Vries, T. Zwemstra, E. Bruls, and P. Regtien, “Built-In Self-Test Methodology for A/D Converters,” in Proc. Europeen Design & Test Conference, 1997, pp. 353-358.
A.K. Lu and G.W. Roberts, “An Analog Multi-Tone Signal Generator for Built-In Self-Test Applications,” in Proc. International Test Conference, 1994, pp. 650-659.
M. Mahoney, DSP-Based Testing of Analog and Mixed-Signal Integrated Circuits, IEEE Computer Society Press, 1987.
M.J. Ohletz, “Hybrid Built-In Self-Test (HBIST) for Mixed Analogue/Digital Integrated Circuits,” in Proc. European Test Conference, 1991, pp. 307-316.
B. Provost and E. Sanchez-Sinencio, “Auto-Calibrating Analog Timer for On-Chip Testing,” in Proc. International Test Conference, 1999, pp. 686-695.
M. Renovell, F. Azaïs, S. Bernard, and Y. Bertrand, “Hardware Resource Minimization for a Histogram-Based ADC BIST,” in Proc. VLSI Test Symposium, 2000, pp. 247-252.
G.W. Roberts and A.K. Lu, Analog Signal Generation for Built-In Self-Test of Mixed-Signal Integrated Circuits, Kluwer Academic Publishers, ISBN 0-7923-9564-6, 1995.
M.F. Toner and G.W. Roberts, “A Frequency Response, Harmonic Distortion, and Intermodulation Distortion Test for BIST of a Sigma-Delta ADC,” IEEE Trans. Circuits & Systems II, vol. 43, no. 8, pp. 608-613, 1996.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Bernard, S., Azaïs, F., Bertrand, Y. et al. On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST. Journal of Electronic Testing 19, 469–479 (2003). https://doi.org/10.1023/A:1024652328578
Issue Date:
DOI: https://doi.org/10.1023/A:1024652328578