Abstract
The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper, while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.
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Dorsch, R., Wunderlich, HJ. Reusing Scan Chains for Test Pattern Decompression. Journal of Electronic Testing 18, 231–240 (2002). https://doi.org/10.1023/A:1014968930415
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DOI: https://doi.org/10.1023/A:1014968930415