Abstract
High-performance, reliable, and robust products with a short development schedule are general design aims. FACE was developed to achieve these goals, including the organization of a design flow, a frequency-driven information analyzer, compiler techniques (code generator and instruction optimization), and a hierarchical object design library. This paper explores the design space of a retargetable compiler and a reconfigurable hardware, which combine both software and hardware reprogrammability. The environment, FACE, we have developed allows us to quickly move the functions between software and hardware in a state of flux. Finally, it generates the application specific integrated processor (ASIP) and a compiler for the new ASIP architecture. The case study is considered which demonstrates the efficiency in ASIP design of FACE.
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Jeng, IH., Lai, F. & Tseng, YD. FACE: Fine-tuned Architecture Codesign Environment for ASIP Development. Design Automation for Embedded Systems 4, 329–351 (1999). https://doi.org/10.1023/A:1008973722314
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DOI: https://doi.org/10.1023/A:1008973722314