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Random Pattern Testability of Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections

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Abstract

Of late some interesting and useful work has been done on the problem of testing logic surrounding embedded memories. This work assumes that the logic surrounding the memory is functionally partitioned and that the different partitions are logically isolated one from the other. This paper expands upon past work using a more flexible design rule which allows feed-forward connections between the data-path Prelogic and Postlogic. The connections are such that there is no feedback from the memory outputs to its inputs, and both the Prelogic and the Postlogic are disconnected from the Address and Control logic. Under this design rule we show the auxiliary circuits used to determine the random pattern testability of faults in the circuitry driving the address inputs and the controls of the two-port memory. The techniques described herein are intended to be used in conjunction with the cutting algorithm for testability measurement in built-in self-test (BIST) designs, but may also be suitable for use with other detection probability tools and simulation tools.

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Authors and Affiliations

  1. ECE Department, New Jersey Institute of Technology, University Heights, Newark, New Jersey, 07102-1982

    Jacob Savir

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  1. Jacob Savir
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Savir, J. Random Pattern Testability of Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections. Journal of Electronic Testing 15, 279–296 (1999). https://doi.org/10.1023/A:1008345026085

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