Abstract
This paper describes a block processing unit in a single-chip MPEG-2 MP@ML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 μm triple-layer metal CMOS cell-base technology at 54 MHz.
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Katayama, Y., Kitsuki, T. & Ooi, Y. A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 22, 59–64 (1999). https://doi.org/10.1023/A:1008173803054
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DOI: https://doi.org/10.1023/A:1008173803054