Abstract
This paper focuses on the design process for reconfigurable architecture. Our contribution focuses on introducing a new temporal partitioning algorithm. Our algorithm is based on typical mathematic flow to solve the temporal partitioning problem. This algorithm optimizes the transfer of data required between design partitions and the reconfiguration overhead. Results show that our algorithm considerably decreases the communication cost and the latency compared with other well known algorithms.
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Ramzi Ayadi received his M. Sc. degree in electronics and microelectronics from the University of Monastir, Tunisia in 2007. He is currently completing his Ph. D. degree at the Electronic and Micro-Electronic Laboratory, Faculty of Sciences of Monastir.
His research interests include high level synthesis, methodologies development for reconfigurables architectures.
Bouraoui Ouni received his licence and his master respectively in 1999 and 2001. He completed his thesis in 2008 from the Faculty of Science of Monastir, Tunisia. Since 2002, he has been an assistant professor in digital electronic at the High Institute of Informatics and Telecommunication of Hamman Sousse and the National School of Engineering of Sousse.
His research interests include high level synthesis and methodologies development for reconfigurable architectures.
Abdellatif Mtibaa is currently professor in micro-electronics and hardware design with Electrical Department at the National School of Engineering of Monastir, Tunisia and head of Circuits Systems Reconfigurable-ENIM-Group at Electronic and Microelectronic Laboratory. He holds a diploma in electrical engineering in 1985 and received his Ph.D. degree in electrical engineering in 2000. He has authored/coauthored over 100 papers in international journals and conferences. He served on the technical program committees for several international conferences. He also served as a co-organizer of several international conferences.
His research interests include system on programmable chip, high level synthesis, rapid prototyping and reconfigurable architecture for real-time multimedia applications.
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Ayadi, R., Ouni, B. & Mtibaa, A. A partitioning methodology that optimizes the communication cost for reconfigurable computing systems. Int. J. Autom. Comput. 9, 280–287 (2012). https://doi.org/10.1007/s11633-012-0645-1
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DOI: https://doi.org/10.1007/s11633-012-0645-1