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Comparative Analysis of Open and Short Defects in Embedded SRAM Using Parasitic Extraction Method for Deep Submicron Technology

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Abstract

The technology advances from the micron level to the Nanometer level. This striking change in the technology with so many factors might influence the embedded device design and its performance. In the fast-growing technology, it is very difficult to find suitable algorithms to test embedded SRAM. It is noticed that while going to deep sub-nano technologies, the existing test methods may not fully satisfy the test results due to the increased number of faults and defects. Scale-down technologies have an impact on the parasitic effects, creating an additional source of faulty behavior, and making the existing test techniques less effective in detecting them. In this paper we propose a new method, taking the parasitic effect into the consideration, which gives the fault information along with its location. In the proposed method we have considered node-to-node open and short defects for different technologies (45 nm, 32 nm, and 7 nm). It is observed that the proposed test method gives 100% fault coverage which is independent of technology variation.

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All simulation results are available with authors.

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Authors and Affiliations

  1. School of Electronics and Electrical Engineering, Lovely Professional University, Phagwara, India

    Venkatesham Maddela & Sanjeet Kumar Sinha

  2. Department of Electronics and Communication Engineering, BVRIT HYDERABAD College of Engineering for Women, Hyderabad, India

    Venkatesham Maddela & Muddapu Parvathi

  3. ni2designs Pvt.Ltd, Pune, India

    Vinay Sharma

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  1. Venkatesham Maddela
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  2. Sanjeet Kumar Sinha
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  4. Vinay Sharma
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Contributions

VM simulated all the results, SKS analyzed the theory behind the simulation result, MP formatted the results and conclusion, and Vinay Sharma plotted and analyzed the results.

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Correspondence to Sanjeet Kumar Sinha.

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Maddela, V., Sinha, S.K., Parvathi, M. et al. Comparative Analysis of Open and Short Defects in Embedded SRAM Using Parasitic Extraction Method for Deep Submicron Technology. Wireless Pers Commun 132, 2123–2141 (2023). https://doi.org/10.1007/s11277-023-10704-w

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