Abstract
DRAM’s are essential for memory-based electronics devices and the usage of RAM is increasing day by day to reach the user's expectation the products are get designed based on low power and portable. The proposed DRAM cell has a separate read and write path for improvement in read and write abilities. Power dissipation is a major issue to solve this issue researchers are focusing on low power circuits and trying to design the circuits with less number of the transistor so that it will consume less amount of power. In this paper, three structures are presently based on MOSFET technology and CNTFET technology. MOSFET model structures are divided into two they are 1.DRAM circuit with Tri-state buffers and 2. DRAM circuit without Tri-state buffers. CNTFET based structure is built with the help of Carbon Nanotube-FET’s and the structure is the same as DRAM without Tri-state buffers. Power analysis, voltage, delay are evaluated with the help of cadence virtuoso and LT spice Tools. The proposed DRAM cell exhibits higher write and reads margins with an improvement compared to conventional cell.
Similar content being viewed by others
Data Availability
All simulation results are available in cadence virtuoso Lab of VLSI Domain under School of Electronics and Electrical Engineering, lovely Professional University, Punjab, India.
References
Asai, S. (1986). Semiconductor memory trends. Proceedings of the IEEE, 74(12), 1623–1635.
Cha, S. Y. (2011). DRAM technology-history & challenges. In Proc. IEDM.
Spessot, A., & Oh, H. (2020). 1T-1C dynamic random access memory status, challenges, and prospects. IEEE Transactions on Electron Devices, 67(4), 1382–1393.
Hwang, C. G. (2002). Semiconductor memories for IT era. In 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315). San Francisco, CA, USA, (vol.1, pp. 24–27).
Rodriguez, N., Gamiz, F., & Cristoloveanu, S. (2010). A RAM memory cell: Concept and operation. IEEE Electron Device Letters, 31(9), 972–974.
Jacob, B., Wang, D., & Ng, S. (2010). Memory systems: Cache, DRAM, disk. Morgan Kaufmann.
Nair, P., Chou, C., & Qureshi, M. K. (2013) A case for refresh pausing in DRAM memory systems. In 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA). Shenzhen, China (pp. 627–638).
Keeth, B., Baker, R. J., Johnson, B., & Lin, F. (2007). DRAM circuit design: Fundamental and high-speed topics (Vol. 13). John Wiley & Sons.
Chander, S., Baishya, S., Sinha, S. K., Kumar, S., Singh, P., Baral, K., Tripathy, M., Singh, A., & Jit, S. (2019). Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs. Elsevier, Superlattices and Microstructures, 131, 30–39.
Garg, S., & Saurabh, S. (2018). Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis. Superlattices and Microstructures, 113, 261–270.
Kim, H. W., & Kwon, D. (2021). Steep switching characteristics of L-shaped tunnel FET with doping engineering. IEEE Journal of the Electron Devices Society, 9, 359–364.
Pindoo, I. A., Sinha, S. K., & Chander, S. (2021). Performance analysis of heterojunction tunnel FET device with variable temperature. Applied Physics A, 127(10), 1–10.
Dash, S., & Mishra, G. P. (2015). A 2D analytical cylindrical gate tunnel FET (CG-TFET) model: Impact of shortest tunneling distance. Advances in Natural Sciences: Nanoscience and Nanotechnology, 6(3), 035005.
Bohr, M., & Elmansy, Y. (1998). Technology for advanced high-performance microprocessors. IEEE Transactions on Electron Devices, 45, 620–625.
Spasova, M. L., Angelov, G. V., Hristov, M. H. (2012). Simulation of 1T DRAM memory cell with verilog-a model of CNTFET in cadence. Annual Journal of Electronics, 6(2), 1–4
Sinha, S. K., & Chaudhury, S. (2013). Impact of oxide thickness on gate capacitance-a comprehensive analysis on MOSFET, nanowire FET, and CNTFET devices. IEEE Transactions on Nanotechnology, 12(6), 958–964.
Raad, B., Nigam, K., Sharma, D., & Kondekar, P. (2016). Dielectric and work function engineered TFET for ambipolar suppression and RF performance enhancement. Electronics Letters, 52(9), 770–772.
Sinha, S. K., & Chaudhury, S. (2012) Simulation and analysis of quantum capacitance in single-gate MOSFET, double-gate MOSFET and CNTFET devices for nanometre regime. In International Conference on Communications, Devices and Intelligent Systems (CODIS), (pp. 157–160).
Huq, S. M. I., Nafreen, M., Rahman, T., & Bhadra, S. (2017). Comparative study of full adder circuit with 32nm MOSFET, DG-FinFET and CNTFET. In 2017 4th International Conference on Advances in Electrical Engineering (ICAEE), (pp. 38–43).
Sinha, S. K., & Chaudhury, S. (2015). Analysis of different parameters of channel material and temperature on threshold of CNTFET. Materials Science in Semiconductor Processing, 31, 431–438.
Saurabh, S., & Kumar, M. J. (2011). Novel attributes of a dual material gate nano scale tunnel field-effect transistor. IEEE Transactions on Electron Devices, 58(2), 404–410.
Chander, S., Sinha, S. K., Kumar, S., Singh, P. K., Baral, K., Singh, K., & Jit, S. (2017). Temperature analysis of Ge/Si heterojunction SOI-tunnel FET. Superlattices and Microstructures, 110, 162–170.
Bhati, I., Chang, M. T., Chishti, Z., Lu, S. L., & Jacob, B. (2015). DRAM refresh mechanisms, penalties, and trade-offs. IEEE on Computers, 65(1), 108–21.
Frank, D. J., Dennard, R. H., Nowak, E., Solomon, P. M., Taur, Y., & Wong, H. S. P. (2001). Device scaling limits of Si MOSFETs and their application dependencies. Proceedings of the IEEE, 89(3), 259–287.
Sinha, S. K., & Chander, S. (2021). Investigation of DC performance of Ge-source pocket silicon-on-insulator tunnel field effect transistor in nano regime. Inderscience, International Journal of Nanoparticles, 13(1), 13–20.
Acknowledgments
This work is supported by DST-SERB, CRG grant, Govt. of India, CRG/2020/006229, dated: 05/04/2021.
Funding
Not applicable.
Author information
Authors and Affiliations
Contributions
All the authors did their contribution in the manuscript for the possible publication.
Corresponding author
Ethics declarations
Conflict of interest
The authors declare that they have no conflict of interest.
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
Springer Nature or its licensor holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
About this article
Cite this article
Addala, D., Sinha, S.K., Gadiparthi, M.C. et al. 1T-DRAM Cell with Different FET Technologies for Low Power Application. Wireless Pers Commun 128, 471–486 (2023). https://doi.org/10.1007/s11277-022-09963-w
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11277-022-09963-w