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VHDL Design for Real Time Motion Estimation Video Applications

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Abstract

The VHDL design code and its implementation using 0.25 μm technology have been demonstrated for the real time video applications. The processing time of a frame running at 400 MHz was estimated to be 8.1 ms for QCIF and CIF Sequences, which accommodates more than 120 frames per second, and this warrant real time video codec. The design was validated and simulated using ModelSim from Mentor Graphics tools, and then verified using both the VHDL testbench and the Matlab® Image processing toolbox. Various alternate search algorithms have been proposed and simulated using Matlab for their real time processing. Skipping “every other column” (SC), and skipping “every other row and column” (SRC) algorithm, “optimal local neighborhood search” (OLNS), and limited-optimal neighborhood search (L-OLNS) have been demonstrated. The microprocessor as a controller is based on RISC processor and it uses pipelining to gain clocking efficiency.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Purdue School of Engineering and Technology, Indiana University Purdue University Indianapolis, 723W Michigan Street, Indianapolis, IN, 46202, USA

    Robert Meagher, Modukuri Sushmitha, Maher E. Rizkalla, Paul Salama & Mohamed El-Sharkawy

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  1. Robert Meagher
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  2. Modukuri Sushmitha
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  3. Maher E. Rizkalla
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  4. Paul Salama
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  5. Mohamed El-Sharkawy
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Correspondence to Maher E. Rizkalla.

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Meagher, R., Sushmitha, M., Rizkalla, M.E. et al. VHDL Design for Real Time Motion Estimation Video Applications. J Sign Process Syst Sign Image Video Technol 57, 339–348 (2009). https://doi.org/10.1007/s11265-008-0300-9

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  • DOI: https://doi.org/10.1007/s11265-008-0300-9

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