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High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse

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Abstract

This paper describes an application-specific instruction set for a configurable processor to accelerate motion-compensated frame rate conversion (MC-FRC) algorithms based on block motion estimation (BME). The paper shows that the key to achieve very high performance when creating new instructions is to leverage, at the same time, parallel computations, data reuse, and efficient cache use. This is supported by concrete examples that demonstrate how it can be done in the case of the two algorithms considered. The new instructions are used to implement two BME algorithms: one implements the full search (FS) block matching algorithm (BMA), while the other implements the One-Dimensional Full Search (ODFS) BMA. The obtained acceleration factors exceed one hundred for the MC-FRC algorithm embedding the FS algorithm and twenty for the ODFS algorithm. The results show that getting such global acceleration is the consequence of combining parallel computations, data reuse, and efficient cache use, not of only one of them.

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Acknowledgements

This work was financially supported by Gennum Corp., the Natural Sciences and Engineering Research Council of Canada and the CFI/SOCRN. The research was done using design tools from Tensilica and Synopsys as distributed by CMC Microsystems.

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Authors and Affiliations

  1. Deparment of Electrical Engineering, Groupe de Recherche en Microélectronique, École Polytechnique de Montréal, Montreal, Canada

    Nicolas Beucher, Normand Bélanger & Yvon Savaria

  2. Deparment of Computer Engineering, Groupe de Recherche en Microélectronique, École Polytechnique de Montréal, Montreal, Canada

    Guy Bois

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  1. Nicolas Beucher
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  2. Normand Bélanger
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  3. Yvon Savaria
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  4. Guy Bois
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Corresponding author

Correspondence to Normand Bélanger.

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Beucher, N., Bélanger, N., Savaria, Y. et al. High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse. J Sign Process Syst Sign Image Video Technol 56, 155–165 (2009). https://doi.org/10.1007/s11265-008-0230-6

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  • DOI: https://doi.org/10.1007/s11265-008-0230-6

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