Abstract
Bounding the Worst-Case Execution Time (WCET) of real-time software requires precise knowledge about the reachable program and hardware states that might be observed at runtime. The analysis of precise cache states is particularly important and challenging. Due to the high cost of cache misses the analysis precision may have an important impact on the obtainable WCET bounds, while the large state space of the cache’s history leads to high analysis complexity. This work explores the use of cache summaries in order to optimize the computation of precise cache states. These cache summaries allow us to pre-compute the impact of executing a portion of a program, typically a function, on the cache state. This allows us, for instance, to skip the analysis of entire functions (including nested function calls) when the cache states within these functions are not relevant for the classification of memory accesses into hits/misses. Furthermore, the summaries can be extended to efficiently compute fully context-sensitive cache states. The summaries then not only allow to derive typical cache hit/miss classifications, but also provide fully context-sensitive cache persistence information.
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References
Aho AV, Lam MS, Sethi R, Ullman JD (2006) Compilers: principles, techniques, and tools, 2nd edn. Addison-Wesley, Boston
Alt M, Ferdinand C, Martin F, Wilhelm R (1996) Cache behavior prediction by abstract interpretation. In: Proceedings of the international symposium on static analysis, Springer, SAS ’96, pp 52–66
Ballabriga C, Casse H (2008) Improving the first-miss computation in set-associative instruction caches. In: Proceedings of the Euromicro conference on real-time systems, IEEE, ECRTS ’08, pp 341–350, https://doi.org/10.1109/ECRTS.2008.34
Ballabriga C, Casse H, Sainrat P (2008) An improved approach for set-associative instruction cache partial analysis. In: Proceedings of the symposium on applied computing, ACM, SAC ’08, pp 360–367, https://doi.org/10.1145/1363686.1363778
Brandner F, Noûs C (2020) Precise and efficient analysis of context-sensitive cache conflict sets. In: Proceedings of the international conference on real-time networks and systems, ACM, RTNS ’20, p 44–55, https://doi.org/10.1145/3394810.3394811
Chattopadhyay S, Roychoudhury A (2011) Scalable and precise refinement of cache timing analysis via model checking. In: Proceedings of the real-time systems symposium, IEEE, RTSS ’11, pp 193–203, https://doi.org/10.1109/RTSS.2011.25
Chu D, Jaffar J, Maghareh R (2016) Precise cache timing analysis via symbolic execution. In: Proceedings of the real-time and embedded technology and applications symposium, RTAS ’16, pp 1–12, https://doi.org/10.1109/RTAS.2016.7461358
Cousot P, Cousot R (1977) Abstract interpretation: a unified lattice model for static analysis of programs by construction or approximation of fixpoints. In: Proceedings of the symposium on principles of programming languages, ACM, POPL ’77, pp 238–252, https://doi.org/10.1145/512950.512973
Cullmann C (2013) Cache persistence analysis: theory and practice. ACM Trans Embed Comput Syst 12(1s):1–25. https://doi.org/10.1145/2435227.2435236
Degasperi P, Hepp S, Puffitsch W, Schoeberl M (2014) A method cache for Patmos. In: Proceedings of the international symposium on object/component-oriented real-time distributed computing, IEEE, ISORC ’14, pp 100–108, https://doi.org/10.1109/ISORC.2014.47
Dvorak DL (2009) NASA study on flight software complexity. Technical excellence initiative, NASA Office of Chief Engineer
Falk H, Altmeyer S, Hellinckx P, Lisper B, Puffitsch W, Rochange C, Schoeberl M, Sørensen RB, Wägemann P, Wegener S (2016) TACLeBench: a benchmark collection to support worst-case execution time research. In: Proceedings of the international workshop on worst-case execution time analysis, Schloss Dagstuhl, OASIcs, vol 55, pp 1–10
Ferdinand C, Wilhelm R (1999) Efficient and precise cache behavior prediction for real-time systems. Real-Time Syst 17(2–3):131–181. https://doi.org/10.1023/A:1008186323068
Hahn S, Reineke J (2018) Design and analysis of SIC: a provably timing-predictable pipelined processor core. In: Proceedings of real-time systems symposium, RTSS ’18, pp 469–481. https://doi.org/10.1109/RTSS.2018.00060
Hepp S, Brandner F (2014) Splitting functions into single-entry regions. In: Proceedings of the international conference on compilers, architecture and synthesis for embedded systems, ACM, CASES ’14, pp 17:1–17:10. https://doi.org/10.1145/2656106.2656128
Huber B, Hepp S, Schoeberl M (2014) Scope-based method cache analysis. In: International workshop on worst-case execution time analysis, Schloss Dagstuhl, OASIcs, vol 39, pp 73–82
Huynh BK, Ju L, Roychoudhury A (2011) Scope-aware data cache analysis for WCET estimation. In: Proceedings of the real-time and embedded technology and applications symposium, IEEE, RTAS ’11, pp 203–212, https://doi.org/10.1109/RTAS.2011.27
Jordan A, Brandner F, Schoeberl M (2013) Static analysis of worst-case stack cache behavior. In: Proceedings of the conference on real-time networks and systems, ACM, RTNS ’13, pp 55–64
Kadota H, Miyake J, Okabayashi I, Maeda T, Okamoto T, Nakajima M, Kagawa K (1987) A 32-bit CMOS microprocessor with on-chip cache and TLB. IEEE J Solid-State Circuits 22(5):800–807
Khedker U, Sanyal A, Karkare B (2009) Data flow analysis: theory and practice, 1st edn. CRC Press, Boca Raton
Li YTS, Malik S (1995) Performance analysis of embedded software using implicit path enumeration. In: Proceedings of the design automation conference, ACM, DAC ’95, pp 456–461, https://doi.org/10.1145/217474.217570
Lv M, Guan N, Reineke J, Wilhelm R, Yi W (2016) A survey on static cache analysis for real-time systems. Leibniz Trans Embed Syst 3(1):05:1-05:48. https://doi.org/10.4230/LITES-v003-i001-a005
Minato Si (1993) Zero-suppressed BDDs for set manipulation in combinatorial problems. In: Proceedings of the international design automation conference, ACM, DAC ’93, pp 272–277. https://doi.org/10.1145/157485.164890
Mishchenko A (2001) An introduction to zero-suppressed binary decision diagrams. University of California, Berkeley, Tech. rep
Mueller F (1994) Static cache simulation and its applications. PhD thesis, Florida State University
Mueller F (2000) Timing analysis for instruction caches. Real-Time Syst 18(2/3):217–247. https://doi.org/10.1023/A:1008145215849
Nagar K, Srikant YN (2017) Refining cache behavior prediction using cache miss paths. ACM Trans Embed Comput Syst 16(4):103:1-103:26. https://doi.org/10.1145/3035541
Naji A, Brandner F (2015) A comparative study of the precision of stack cache occupancy analyses. In: Proceedings of the junior researcher workshop on real-time computing, JRWRTC ’15, pp 13–16
Patil K, Seth K, Mueller F (2004) Compositional static instruction cache simulation. In: Proceedings of the conference on languages, compilers, and tools for embedded systems, ACM, LCTES ’04, pp 136–145. https://doi.org/10.1145/997163.997183
Puschner PP, Schedl AV (1997) Computing maximum task execution times—a graph-based approach. Real-Time Syst 13(1):67–91. https://doi.org/10.1023/A:1007905003094
Rakib A, Parshin O, Thesing S, Wilhelm R (2004) Component-wise instruction-cache behavior prediction. In: Proceedings of automated technology for verification and analysis, Springer, ATVA ’04, pp 211–229
Rashid SA, Nelissen G, Hardy D, Akesson B, Puaut I, Tovar E (2016) Cache-persistence-aware response-time analysis for fixed-priority preemptive systems. In: Proceedings of the Euromicro conference on real-time systems, ECRTS’16, pp 262–272. https://doi.org/10.1109/ECRTS.2016.25
Reineke J, Grund D (2013) Sensitivity of cache replacement policies. ACM Trans Embed Comput Syst. https://doi.org/10.1145/2435227.2435238
Schoeberl M, Schleuniger P, Puffitsch W, Brandner F, Probst C, Karlsson S, Thorn T (2011) Towards a time-predictable dual-issue microprocessor: The patmos approach. In: Proceedings of bringing theory to practice: predictability and performance in embedded systems, OASICS, vol 18, pp 11–21
Schoeberl M, Brandner F, Hepp S, Puffitsch W, D P (2013) Patmos reference handbook. Technical University of Denmark. http://patmos.compute.dtu.dk/patmos_handbook.pdf
Schoeberl M, Puffitsch W, Hepp S, Huber B, Prokesch D (2018) Patmos: a time-predictable microprocessor. Real-Time Syst 54(2):389–423. https://doi.org/10.1007/s11241-018-9300-4
Smith AJ (1982) Cache memories. ACM Comput Surv 14(3):473–530. https://doi.org/10.1145/356887.356892
Stein IJ (2010) ILP-based path analysis on abstract pipeline state graphs. PhD thesis, Universität des Saarlandes
Stock G, Hahn S, Reineke J (2019) Cache persistence analysis: finally exact. In: Proceedings of the real-time systems symposium, RTSS ’19, pp 481–494
Theiling H, Ferdinand C (1998) Combining abstract interpretation and ILP for microarchitecture modelling and program path analysis. In: Proceedings of the real-time systems symposium, IEEE, RTSS ’98, pp 144–153
Touzeau V, Maïza C, Monniaux D, Reineke J (2017) Ascertaining uncertainty for efficient exact cache analysis. In: Computer aided verification, Springer, CAV ’17, pp 22–40
Touzeau V, Maïza C, Monniaux D, Reineke J (2019) Fast and exact analysis for LRU caches. Proc ACM Program Lang 3(POPL):54:1-54:29. https://doi.org/10.1145/3290367
Acknowledgements
The author would like to thank Thomas Robert for sharing his understanding on BDDs/ZDDs and the associated libraries as well as Mihail Asavoae for the insight-full discussions leading up to this work. The author would like to thank in particular Amine Naji for his contributions to the Odyssey WCET analysis framework.
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Brandner, F., Noûs, C. Precise, efficient, and context-sensitive cache analysis. Real-Time Syst 58, 36–84 (2022). https://doi.org/10.1007/s11241-021-09372-5
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DOI: https://doi.org/10.1007/s11241-021-09372-5