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An extensible architecture of 32-bit ALU for high-speed computing in QCA technology

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Abstract

The technological advancements in the semiconductor industry have significantly improved over the years. However, Complementary Metal Oxide Semiconductor (CMOS) technology has its fabrication limitations. This requires new methods and materials for computation at the nanometric level. Quantum-dot cellular automata (QCA) is a revolutionary method that can sidestep CMOS’s practical limits. ALU being the key component in processor design must be optimized for high-speed processing and computation of data to meet the current requirements of portable gadgets. In this paper, a modular approach and extensible architecture for Arithmetic Logic Unit (ALU) design are proposed for high-speed computation. The design of the ALU is extended to perform the computation on multiple bits. The proposed design of the ALU performs 8 operations (four arithmetic, four logical) up to 32-bit computation. The architecture of ALU is made of modular blocks of XOR, XNOR, Adder, and Multiplexer instead of conventional gates. The QCA layout of the 32-bit ALU has 23,189 cells in a 62.68 µm2 area with a delay of 34 clock cycles. The energy dissipation of a 32-bit ALU is 300 meV estimated using coherence vector energy simulation in QCA Designer-E. The delay of an N-bit ALU is calculated by the formula N + 2, which shows the delay efficiency of the proposed architecture of ALU design.

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  1. Department of Electrical & Electronics Engineering, Shri Vaishnav Vidyapeeth Vishwavidyalaya, Indore, MP, India

    Nilesh Patidar & Namit Gupta

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  1. Nilesh Patidar
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Patidar, N., Gupta, N. An extensible architecture of 32-bit ALU for high-speed computing in QCA technology. J Supercomput 78, 19605–19627 (2022). https://doi.org/10.1007/s11227-022-04608-y

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