Abstract
The Controller model is a heterogeneous parallel programming model implemented as a library. It transparently manages the coordination, communication and kernel launching details on different heterogeneous computing devices. It exploits native or vendor specific programming models and compilers, such as OpenMP, CUDA or OpenCL, thus enabling the potential performance obtained by using them. This work discusses the integration of FPGAs in the Controller model, using high-level synthesis tools and OpenCL. A new Controller backend for FPGAs is presented based on a previous OpenCL backend for GPUs. We discuss new configuration parameters for FPGA kernels and key ideas to adapt the original OpenCL backend while maintaining the portability of the original model. We present an experimental study to compare performance and development effort metrics obtained with the Controller model, Intel oneAPI and reference codes directly programmed with OpenCL. The results show that using the Controller library has advantages and drawbacks compared with Intel oneAPI, while compared with OpenCL it highly reduces the programming effort with negligible performance overhead.
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This research has been partially supported by the Spanish Ministerio de Economía, Industria y Competitividad and by the ERDF program of the European Union, PCAS Project (TIN2017-88614-R); by Junta de Castilla y Leon - FEDER Grants, PROPHET and PROPHET-2 Projects (VA082P17, VA226P20); MECD (Beca de Colaboración, Spain), ScottishPower Masters Scholarship, and Salvador de Madariaga/Fulbright Scholar Grant (PRX17/00674).
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Rodriguez-Canal, G., Torres, Y., Andújar, F.J. et al. Efficient heterogeneous programming with FPGAs using the Controller model. J Supercomput 77, 13995–14010 (2021). https://doi.org/10.1007/s11227-021-03792-7
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DOI: https://doi.org/10.1007/s11227-021-03792-7