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Design trade-offs for emerging HPC processors based on mobile market technology

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Abstract

High-performance computing (HPC) is at the crossroads of a potential transition toward mobile market processor technology. Unlike in prior transitions, numerous hardware vendors and integrators will have access to state-of-the-art processor designs due to Arm’s licensing business model. This fact gives them greater flexibility to implement custom HPC-specific designs. In this paper, we undertake a study to quantify the different energy-performance trade-offs when architecting a processor based on mobile market technology. Through detailed simulations over a representative set of benchmarks, our results show that: (i) a modest amount of last-level cache per core is sufficient, leading to significant power and area savings; (ii) in-order cores offer favorable trade-offs when compared to out-of-order cores for a wide range of benchmarks; and (iii) heterogeneous configurations help to improve processor performance and energy efficiency.

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Notes

  1. The Xeon Phi product line has been discontinued.

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Acknowledgements

This work has been partially supported by the European HiPEAC Network of Excellence, by the Spanish Ministry of Economy and Competitiveness (contract TIN2015-65316-P), and by the Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272). The Mont-Blanc project receives funding from the EUs H2020 Framework Programme (H2020/2014-2020) under Grant Agreements Nos. 671697 and 779877. M. Moreto has been partially supported by the Spanish Ministry of Economy, Industry and Competitiveness under Ramon y Cajal fellowship number RYC-2016-21104. M. Casas has been partially supported by the Secretary for Universities and Research of the Ministry of Economy and Knowledge of the Government of Catalonia and the Cofund programme of the Marie Curie Actions of the European Union (Contract 2013 BP B 00243). Finally, A. Armejach has been partially supported by the Spanish Ministry of Economy, Industry and Competitiveness under Juan de la Cierva postdoctoral fellowship number FJCI-2015-24753.

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  1. Barcelona Supercomputing Center, Barcelona, Spain

    Adrià Armejach, Marc Casas & Miquel Moretó

  2. Universitat Politècnica de Catalunya, Barcelona, Spain

    Adrià Armejach & Miquel Moretó

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  1. Adrià Armejach
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Correspondence to Adrià Armejach.

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Armejach, A., Casas, M. & Moretó, M. Design trade-offs for emerging HPC processors based on mobile market technology. J Supercomput 75, 5717–5740 (2019). https://doi.org/10.1007/s11227-019-02819-4

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