Abstract
The number of cores on the chip increases rapidly; therefore, scalability is the most important design choice. Mesh-based Networks-on-Chip (NoC) are the most widely used topologies as a scalable alternative for traditional shared bus in many-core chips today. As the NoCs diameter increases, the low-latency communication between cores is becoming more important to ensure sustained scalability, and higher performance. In the ideal network, the low-load network latency between a source and destination is almost equal to single cycle. In this work, we propose a router for network-on-chip called Bypass router that leads to create a single-cycle data path all the way from the source to the destination. We do not use any additional control links in the network; instead the proposed router is compatible with all topologies and deterministic routing algorithm. We also propose a new routing algorithm to use the advantages of our router design. The area consumption is also reduced on \( 4\times 4, 8\times 8, 16\times 16 \) mesh topologies, compared to SMART network (Krishna et al. IEEE 19th international symposium on high performance computer architecture (HPCA2013), 2013). System simulations with Noxim simulators demonstrate at mean 60 % reduction in latencies across synthetic traffic patterns compared to a baseline router.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Krishna T et al (2013) Breaking the on-chip latency barrier using SMART. In: IEEE 19th international symposium on high performance computer architecture (HPCA2013)
Marculescu R et al (2009) Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives. Comput-Aided Des Integr Circ Syst IEEE Trans 28(1):3–21
Murali S, De Micheli G (2004) Bandwidth-constrained mapping of cores onto NoC architectures. In: Proceedings of the conference on Design, automation and test in Europe, vol 2. IEEE Computer Society
Hu J, Marculescu R (2003) Energy-aware mapping for tile-based NoC architectures under performance constraints. In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ACM
Grot B et al (2009) Express cube topologies for on-chip interconnects. High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th international symposium on IEEE
Kim J, Dally WJ, Abts D (2007) Flattened butterfly: a cost-efficient topology for high-radix networks. ACM SIGARCH Comput Archit News 35(2):126–137
Kao Y-H et al (2011) CNoC: high-radix clos network-on-chip. Comput-Aided Des Integr Circ Syst IEEE Trans 30(12):1897–1910
Hoskote Y et al (2007) A 5-GHz mesh interconnect for a teraflops processor. IEEE Micro 27(5):51–61
Howard J et al (2010) A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS. Solid-state circuits conference digest of technical papers (ISSCC), 2010 IEEE international, IEEE
Glass CJ, Ni LM (1992) The turn model for adaptive routing. ACM SIGARCH Comput Archit News 20(2):278–287
Chiu G-M (2000) The odd–even turn model for adaptive routing. Parallel Distrib Syst IEEE Trans 11(7):729–738
Boura YM, Das CR (1994) Efficient fully adaptive wormhole routing in n-dimensional meshes. Distributed computing systems, 1994. In: Proceedings of the 14th international conference on IEEE
Li M, Zeng Q-A, Jone W-B (2006) DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip. In: Proceedings of the 43rd annual design automation conference, ACM
Jain TNK et al (2010) Asynchronous bypass channels: improving performance for multi-synchronous NoCs. In: 2010 Fourth ACM/IEEE international symposium on Networks-on-Chip (NOCS). IEEE
Rodrigo S et al (2009) Efficient implementation of distributed routing algorithms for NoCs. IET Comput Digit Tech 3(5):460–475
Matsutani H et al (2009) Prediction router: yet another low latency on-chip router architecture. In: IEEE 15th international symposium on high performance computer architecture. HPCA 2009. IEEE, pp 367–378
Kumar A, Peh L-S, Jha NK (2008) Token flow control. In: Proceedings of the 41st annual IEEE/ACM international symposium on Microarchitecture. IEEE Computer Society
Jerger NE, Peh L-S (2009) On-chip networks. Morgan and cLaypool, Cambridge
Badri S, Holsmark R, Kumar S (2012) Junction based routing: a scalable technique to support source routing in large NoC platforms. In: Proceedings of the 5th international workshop on Network on chip architectures, ACM
Dally WJ, Towles BP (2004) Principles and practices of interconnection networks. Elsevier, Amsterdam
Fazzino F, Palesi M, Patti D (2008) Noxim: network-on-chip simulator. http://sourceforge.net/projects/noxim
Kahng AB et al (2009) ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration. In: Proceedings of the conference on Design, automation and test in Europe. European Design and Automation Association
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Fadakar Noghondar, A., Reshadi, M. A low-cost and latency bypass channel-based on-chip network. J Supercomput 71, 3770–3786 (2015). https://doi.org/10.1007/s11227-015-1466-0
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11227-015-1466-0