Revisiting reorder buffer architecture for next generation high performance computing

1. Folegnani D, Gonzalez A (2001) Energy-effective issue logic. In: The proceedings of the IEEE international symposium on computer architecture (ISCA)

   Google Scholar 

2. Nan H, Kim KK, Wang W, Choi K (2011) Dynamic voltage and frequency scaling for power-constrained design using process voltage and temperature sensor circuits. J Inf Process Syst 7(1)

3. Åsberg M, Nolte T, Pettersson P Prototyping and code synthesis of hierarchically scheduled systems using TIMES. J Converg 1(1):75–84

4. Sathappan OL, Chitra P, Venkatesh P, Prabhu M Modified genetic algorithm for multiobjective task scheduling on heterogeneous computing system. Int J Inf Technol, Commun Converg 1(2):146–158

5. Ye Y, Li X, Wu B, Li Y A comparative study of feature weighting methods for document co-clustering. Int J Inf Technol, Commun Converg 1(2):206–220

6. Fisher JD (2009) Design and implementation of low power reorder buffer. Dissertation of University of Texas at San Antonio, 77 p

7. Cristal A, Santana O, Cazorla F, Galluzzi M, Ramirez T, Pericas M, Valero M (2005) Kilo-instruction processors: overcoming the memory wall. IEEE micro

   Google Scholar 

8. Kirman N, Kirman M, Chaudhuri M, Martinez J (2005) Checkpointed early load retirement. In: Proceedings of the international symposium on high-performance computer architecture (HPCA)

   Google Scholar 

9. Martinez J, Renau J, Huang M, Prvulovic M, Torrellas J (2002) Cherry: Checkpointed early resource recycling in our-of-order microprocessors. In: Proceedings of the IEEE international symposium on microarchitecture (MICRO)

   Google Scholar 

10. Dundas J, Mudge T (1997) Improving data cache performance by pre-executing instructions under a cache miss. In: Proceedings of the ACM international conference on supercomputing (ICS), July 1997

    Google Scholar 

11. Mutlu O, Stark J, Wilkerson C, Patt YN (2003) Runahead execution: An alternative to very large instruction windows for out-of-order processors. In: Proceedings of the IEEE international symposium on high performance computer architecture (HPCA), February 2003, pp 129–140

    Google Scholar 

12. Kucuk G, Ergin O, Ponomarev D, Ghose K (2003) Distributed reorder buffer schemes for low power. In: International conference on computer design (ICCD)

    Google Scholar 

13. Smith JE (1985) Implementation of precise interrupts in pipelined processors. The anatomy of a microprocessor: A system perspective. IEEE CS Press, Los Alamitos

    Google Scholar 

14. Brown JA, Porter L, Tullsen DM (2011) Fast thread migration via cache working set prediction. In: International symposium on high performance computer architecture (HPCA)

    Google Scholar 

15. Mehrara M, Hsu PC, Samadi M, Mahlke S (2011) Dynamic parallelization of JavaScript applications using an ultra-lightweight speculation mechanism. In: International symposium on high performance computer architecture (HPCA)

    Google Scholar 

16. Sima D (2000) The design space of register renaming techniques. IEEE micro

    Google Scholar 

17. Obaidat MS, Dhurandher SK, Gupta D, Gupta N, Asthana A (2010) DEESR, dynamic energy efficient and secure routing protocol for wireless sensor networks in urban environments. J Inf Process 6(3)

18. Jerbi K, Wipliez M, Raulet M, Babel M, Déforges O, Abid M Automatic method for efficient hardware implementation from RVC-CAL dataflow: A LAR coder baseline case study. J Converg 1(1):85–92

Download references