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E3C Techniques for Protecting NAND Flash Memories

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Abstract

Due to the rapid technology scaling and increasing program/erase cycles, the raw bit error rate (RBER) in NAND flash memory keeps increasing rapidly. This dilemma seriously incurs reliability issues. The traditional error correction codes (ECCs) with stronger protection capability are usually equipped for all flash pages as a solution to maintain the mandatory yield and reliability levels. However, the growth of RBER is exponentially proportional to the number of induced P/E cycles and the distributions of errors are usually uneven. Therefore, the conventional uniform ECC protection based on the worst scenario of fault distributions might incur unnecessary hardware and latency overhead. Moreover, the overlong ECC check bits might be stored in two different flash pages. Therefore, two flash read/program operations are required for reading/programming a codeword. To cure these drawbacks, the ECC Caching (E3C) techniques are proposed in this paper. The main idea is to upgrade the ECC protection levels for flash pages when their correction slack is below the specified threshold. An ECC Cache containing the ECC CAM and the ECC SRAM is used for accessing and storing extra check bits, respectively. The corresponding repair flow and hardware architecture are also proposed. According to simulation results, we can enhance the reliability and yield of flash memories significantly with negligible hardware cost.

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  1. National Taiwan University of Science and Technology, Taipei, Taiwan

    Shyue-Kung Lu & Zeng-Long Tsai

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  1. Shyue-Kung Lu
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Correspondence to Shyue-Kung Lu.

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Lu, SK., Tsai, ZL. E3C Techniques for Protecting NAND Flash Memories. J Electron Test 39, 487–500 (2023). https://doi.org/10.1007/s10836-023-06075-6

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