Nothing Special   »   [go: up one dir, main page]
Skip to main content

Advertisement

Springer Nature Link
Log in

New Light Weight Threshold Voltage Defined Camouflaged Gates for Trustworthy Designs

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

The outsourcing of the IC fabrication process introduces the security vulnerabilities into the design. An attacker can exploit them to extract the functionality using image processing-based reverse engineering and can also mount the various attacks such as hardware Trojan, piracy, overbuilding, etc. Various dummy contacts and Threshold Voltage Defined (TVD) logic-based layout camouflaging techniques are presented that can deceive the attacker into incorrectly interpreting the functionality of the camouflaged gate. The existing dummy contact-based techniques require large overhead and provide poor security whereas, the TVD logic-based camouflaging techniques increase the security at the cost of large area and energy overhead. Therefore, in this paper, new light weight TVD static and dynamic logic (TVD-SL and TVD-DL) based camouflaged gates are proposed. The proposed TVD-SL/DL gates have same physical structure and provide the functionality of several standard gates by implanting different threshold voltages during manufacturing. Further, various simplified TVD-SL/DL gates are also proposed to achieve the overhead and security trade-off. To evaluate the efficacy, the proposed TVD logic gates are implemented using 32nm PTM library and simulated using the HSPICE simulator. The simulation results show that the proposed TVD-SL-based gates on an average reduce 35.49%, 59.18% and 72.05% whereas the proposed TVD-DL reduces 54.84%, 84.18% and 82.30% area, power and delay respectively over the existing. Further, on an average, the proposed TVD-DL-based camouflaged gates require 56% less power over the standard gates. Due to the low-cost and high energy efficiency, the proposed logic gates are best suited for the development of secure and portable devices for the Internet of Things applications.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10

Similar content being viewed by others

References

  1. Chakraborty RS, Bhunia S (2009) Harpoon: an obfuscation-based soc design methodology for hardware protection. IEEE Trans Comput Aided Des Integr Circuits Syst 28(10):1493–1502

    Article  Google Scholar 

  2. Chipwork Intel’s 22-nm Tri-gate Transistors Exposed. Available: http://www.chipworks.com/blog/technologyblog/2012/04/23/intels-22-nm-trigate-transistors-exposed/

  3. Chow L-W, Baukus JP, Clark MW Jr (2002) Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide, July 25. US Patent 20,020, 096, 776

  4. Chow L-W, Baukus JP, Clark WM Jr (2007) Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide, November 13. US Patent 7, 294, 935

  5. Cocchi RP, Baukus JP, Wang BJ, Chow LW, Ouyang P (2012) Building block for a secureCMOS logic cell library, February 7. US Patent 8,111, 089

  6. Cocchi RP, Baukus JP, Chow LW, Wang BJ (2014) Circuit camouflage integration for hardware ip protection. In: Proceedings 51st ACM annual design automation conference, pp 1–5

  7. Collantes MIM, Massad ME, Garg S (2016) Threshold-dependent camouflaged cells to secure circuits against reverse engineering attacks. In: Proceedings IEEE computer society annual symposium on VLSI (ISVLSI), pp 443–448

  8. Degate [Online]. Available: http://www.degate.org/documentation/

  9. Dupuis S, Ba P-S, Natale GD, Flottes M-L, Rouzeyre B (2014) A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans. In: Proceedings IEEE 20th International On-Line Testing Symposium (IOLTS), pp 49– 54

  10. Erbagci B, Erbagci C, Akkaya NEC, Mai K (2016) A secure camouflaged threshold voltage defined logic family. In: Proceedings IEEE international symposium on hardware oriented security and trust (HOST), pp 229–235

  11. International chamber of commerce, Impacts of counterfeiting and piracy to reach us $1.7 trillion by 2015 (2011) [Online]. Available: http://www.iccwbo.org/News/Articles/2011/Impacts-ofcounterfeiting-and-piracy-to-reach-US$1-7-trillion-by-2015/

  12. Karam R, Hoque T, Ray S, Tehranipoor M, Bhunia S (2017) Mutarch: Architectural diversity for fpga device and ip security. In: Proceedings 22nd IEEE Asia and South Pacific design automation conference (ASP-DAC), pp 611–616

  13. Li Meng, Shamsi Kaveh, Meade Travis, Zhao Zheng, Bei Yu, Jin Yier, Pan David Z (2016) Provably secure camouflaging strategy for ic protection. In: Proceedings IEEE/ACM international conference on computer-aided design (ICCAD), pp 1–8

  14. Liu D, Cunxi Y, Zhang X, Holcomb D (2016) Oracle-guided incremental sat solving to reverse engineer camouflaged logic circuits. In: Proceedings IEEE international conference on design, automation & Test in Europe, pp 433–438

  15. Massad ME, Garg S, Tripunitara MV (2015) Integrated circuit (IC) decamouflaging: Reverse engineering camouflaged ICs within minutes. In: Proceedings 22nd Annual Network and Distributed System Security Symposium (NDSS), San Diego, California, USA, pp 1–14

  16. Mentor Graphics Tanner EDA Tool (2017) [Online]. Available: https://www.mentor.com/tannereda/s-edit/

  17. Nirmala IR, Vontela D, Ghosh S, Iyengar A (2016) A novel threshold voltage defined switch for circuit camouflaging. In: Proceedings 21th IEEE European test symposium (ETS), pp 1–2

  18. Predictive Technology Model (PTM) Library (2017) [Online]. Available: http://ptm.asu.edu/

  19. Rajendran J, Sam M, Sinanoglu O, Karri R (2013) Security analysis of integrated circuit camouflaging. In: Proceedings ACM SIGSAC conference on Computer & communications security, pp 709–720

  20. Rajendran J, Sinanoglu O, Karri R (2013) VLSI testing based security metric for IC camouflaging, pp 1–4

  21. Rostami M, Koushanfar F, Karri R (2014) A primer on hardware security: Models, methods, and metrics. Proc IEEE 102(8):1283–1295

    Article  Google Scholar 

  22. SEMI (2008) Innovation is at risk as semiconductor equipment and materials industry loses up to $4 billion annually due to ip infringement. [Online]. Available: https://www.semi.org/en/Press/P043775

  23. Subramanyan P, Ray S, Malik S (2015) Evaluating the security of logic encryption algorithms. In: Proceedings IEEE international symposium on hardware oriented security and trust (HOST), pp 137–143

  24. Synopsys HSPICE Circuit Simulator (2017) [Online]. Available: https://www.synopsys.com/verification/ams-verification/circuit-simulation/hspice.html/

  25. TAEUS [Online]. Available: http://www.taeus.com/taeus-services/ip-litigation-services/reverse-engineering/

  26. Wang X, Zhou Q, Cai Y, Gang Q (2016) Is the secure IC camouflaging really secure? In: Proceedings IEEE international symposium on circuits and systems (ISCAS), pp 1710–1713

  27. Xiao K, Forte D, Jin Y, Karri R, Bhunia S, Tehranipoor M (2016) Hardware trojans: lessons learned after one decade of research. ACM Trans Des Autom Electron Syst 22(1):6

    Article  Google Scholar 

  28. Yasin M, Sinanoglu O, Rajendran J (2017) Testing the trustworthiness of IC testing: An oracle-less attack on IC camouflaging. IEEE Transactions on Information Forensics and Security. (In Press)

Download references

Author information

Authors and Affiliations

  1. ABV- Indian Institute of Information Technology and Management, Gwalior, India

    Vijaypal Singh Rathor, Bharat Garg & G. K. Sharma

Authors
  1. Vijaypal Singh Rathor
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Bharat Garg
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. G. K. Sharma
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Vijaypal Singh Rathor.

Additional information

Responsible Editor: S. Bhunia

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Rathor, V.S., Garg, B. & Sharma, G.K. New Light Weight Threshold Voltage Defined Camouflaged Gates for Trustworthy Designs. J Electron Test 33, 657–668 (2017). https://doi.org/10.1007/s10836-017-5683-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-017-5683-8

Keywords

Search

Navigation