Nothing Special   »   [go: up one dir, main page]
Skip to main content
Springer Nature Link
Log in

Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

By adding a few logic gates and one or two modeling flip-flops to the circuit under test (CUT), we create a detection or diagnostic automatic test pattern generation (ATPG) model of transition delay faults usable by a conventional single stuck-at fault test pattern generator. Given a transition delay fault pair, the diagnostic ATPG model can either find an exclusive test or prove the equivalence of the fault pair. Our work offers advantages over existing work. First, the detection of a transition delay fault or the diagnosis of a fault pair can be modeled in only one instead of two or four time-frames of the CUT. Second, an exclusive test can be generated under either launch off capture (LOC) or launch off shift (LOS) mode for a full-scan sequential circuit. Third, the proposed ATPG models can be expanded into two time frames to facilitate the use of combinational ATPG tools, though with lower modeling complexity than was possible before. As a result, the percentage of distinguished transition delay fault pairs is larger and the proposed automatic exclusive test generation system is more time-efficient.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15

Similar content being viewed by others

References

  1. Agrawal P, Agrawal V, Seth S. (1993) Generating tests for delay faults in nonscan circuits. IEEE Des. Test Comput. 10 (1):20–28

    Article  Google Scholar 

  2. Agrawal VD, Baik DH, Kim YC, Saluja KK (2003) Exclusive test and its applications to fault diagnosis. In: Proc. 16th international conf. VLSI design, pp 143–148

  3. Ahmed N, Ravikumar CP, Tehranipoor M, Plusquellic J (2005) At-speed transition fault testing with low speed scan enable. In: Proc. 23rd IEEE VLSI test symposium, pp 42–47

  4. Ahmed N, Tehranipoor M, Ravikumar CP, Butler KM (2007) Local at-speed scan enable generation for transition fault testing using low-cost testers. IEEE Trans Comput-Aided Des 26 (5):896–906

    Article  Google Scholar 

  5. Amyeen ME, Fuchs WK, Pomeranz I, Boppana V (2003) Fault equivalence identification in combinational circuits using implication and evaluation techniques. IEEE Trans Comput-Aided Des 22 (7):922–936

    Article  Google Scholar 

  6. Bhatti NK, Blanton RD (2006) Diagnostic test generation for arbitrary faults. In: Proc. international test conf., pp. 1–9. Paper 19.2

  7. Brglez F, Bryan D, Kozminski K (1989) Combinational profiles of sequential benchmark circuits. In: Proc. IEEE international symposium on circuits and systems, pp 1929–1934

  8. Brglez F, Fujiwara H (1985) A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran. In: Proc. IEEE international symposium on circuits and systems, pp 677–692

  9. Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Springer

  10. Camurati P, Medine D, Prinetto P, Reorda MS (1990) A diagnostic test pattern generation algorithm. In: Proc. international test conf., pp 52–58

  11. Chen SC, Jou JM (1997) Diagnostic fault simulation for synchronous sequential circuits. IEEE Trans Comput-Aided Des 16 (3):299–308

    Article  Google Scholar 

  12. Chess B, Larrabee T (1999) Creating small fault dictionaries. IEEE Trans Comput-Aided Des 18 (3):346–356

    Article  Google Scholar 

  13. Doshi AS (2006) Independence fault collapsing and concurrent test generation. Master’s thesis, Auburn University, ECE Dept.

  14. Doshi AS, Agrawal VD (2005) Independence fault collapsing. In: Proc. 9th VLSI design and test symp., 357–364

  15. Gruning T, Mahlstedt U, Koopmeiners H (1991) DIATEST: a fast diagnostic test pattern generator for combinational circuits. In: Proc. IEEE international conf. computer-aided design, pp 194– 197

  16. Han C, Singh A (2014) On the testing of hazard activated open defects. In: Proc. international test conf., pp 1–6, Paper 1.2

  17. Hartanto I, Boppana V, Fuchs WK (1996) Diagnostic fault equivalence identification using redundancy information & structural analysis. In: Proc. international test conf., pp 20–25

  18. Higami Y, Kurose Y, Ohno S, Yamaoka H, Takahashi H, Takamatsu Y, Shimizu Y, Aikyo T (2009) Diagnostic test generation for transition faults using a stuck-at ATPG tool. In: Proc. international test conf., pp 1–9, Paper 16.3

  19. Higami Y, Saluja KK, Takahashi H, Kobayashi SY, Takamatsu Y (2006) Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. In: Proc. Asia and South Pacific conference on design automation, pp 659– 664

  20. Huisman LM (2006) Diagnosing arbitrary defects in logic designs using single location at a time (SLAT). IEEE Trans Comput-Aid Des 23 (1):91–101

    Article  Google Scholar 

  21. Iyengar VS, Rosen BK, Waicukauski JA (1990) On computing the sizes of detected delay faults. IEEE Trans Comput-Aided Des 9 (3):299–312

    Article  Google Scholar 

  22. Kajihara S, Taniguchi K, Miyase K, Pomeranz I, Reddy SM (2002) Test data compression using don’t-care identification and statistical encoding. In: Proc. 11th IEEE Asian test symposium, pp 67–72

  23. Kajihara S, Taniguchi K, Pomeranz I, Reddy SM (2002) Test data compression using don’t-care identification and statistical encoding, In: Proc. first IEEE international workshop on electronic design, test and applications, pp 413–416

  24. Kantipudi KR (2007)Minimizing N-detect tests for combinational circuits. Master’s thesis, Auburn University, ECE Dept.

  25. Kantipudi KR, Agrawal VD (2007) A reduced complexity algorithm for minimizing N-detect tests. In: Proc. 20th international conf. VLSI design, pp 492–497

  26. Kavousianos X, Chakrabarty K (2011) Generation of compact stuck-at test sets targeting unmodeled defects. IEEE Trans Comput-Aided Des 30 (5):787–791

    Article  Google Scholar 

  27. Lavo DB, Larrabee T (2001) Making cause-effect cost effective: low-resolution fault dictionaries. In: Proc. international test conf., pp 278–286

  28. Lin Y, Lu F, Cheng KT (2007) Multiple-fault diagnosis based on adaptive diagnostic test pattern generation. IEEE Trans Comput-Aided Des 26 (5):932–942

    Article  Google Scholar 

  29. Lin YC, Cheng KT (2006) Multiple-fault diagnosis based on single-fault activation and single-output observation. In: Proc. design, automation and test in Europe, pp 424–429

  30. Majhi AK, Agrawal VD, Jacob J, Patnaik LM (2000) Line coverage of path delay faults. IEEE Trans VLSI Syst 8 (5):610–614

    Article  Google Scholar 

  31. McCluskey EJ, Tseng CW (2000) Stuck-fault tests vs. actual defects. In: Proc international test conf., pp 336–343

  32. Mentor Graphics (2004) FastScan and FlexTest Reference Manual

  33. Mentor Graphics (2009) DFTAdvisor Reference Manual

  34. Pomeranz I, Reddy SM (1992) On the generation of small dictionaries for fault location. In: Proc. IEEE/ACM international conference on computer-aided design, pp 272–279

  35. Pomeranz I, Reddy SM (2000) A diagnostic test generation procedure for synchronous sequential circuits based on test elimination by vector omission for synchronous sequential circuits. IEEE Trans. Comput-Aided Des 19 (5):589–600

    Article  Google Scholar 

  36. Pomeranz I, Reddy SM (2007) Diagnostic test generation based on subsets of faults. In: Proc. 12th IEEE European test symp., pp 151–158

  37. Pomeranz I, Reddy SM, Venkataraman S (2007) z-diagnosis: a framework for diagnostic fault simulation and test generation utilizing subsets of outputs. IEEE Trans Comput-Aided Des 26 (9):1700–1712

    Article  Google Scholar 

  38. Pramanick AK, Reddy SM (1997) On the fault coverage of gate delay fault detecting tests. IEEE Trans Comput-Aided Des 16 (1):78–94

    Article  Google Scholar 

  39. Python https://www.python.org/download/releases/3.4.1/. Accessed July 1 2014

  40. Ryan PG, Fuchs WK, Pomeranz I (1993) Fault dictionary compression and equivalence class computation for sequential circuits. In: Proc. IEEE/ACM international conference on computer-aided design, pp 508–511

  41. Sandireddy RKKR (2005) Hierarchical fault collapsing for logic circuits. Master’s thesis, Auburn University, ECE Dept.

  42. Sandireddy RKKR, Agrawal VD (2005) Diagnostic and detection fault collapsing for multiple output circuits. In: Proc. design, automation and test in Europe, pp 1014–1019

  43. Shukoor MA (2009) Fault detection and diagnostic test set minimization. Master’s thesis, Auburn University, ECE Dept.

  44. Shukoor MA, Agrawal VD (2009) A two phase approach for minimal diagnostic test set generation. In: Proc. European test symp., pp 115–120

  45. Shukoor MA, Agrawal VD (2012) Diagnostic test set minimization and full-response fault dictionary. J Electron Test Theory Appl 28 (2):177–187

    Article  Google Scholar 

  46. Veneris A, Chang R, Abadir MS, Amiri M (2004) Fault equivalence and diagnostic test generation using ATPG. In: Proc. international symposium on circuits and systems, pp V–221–V–224

  47. Venkataraman S, Hartanto I, Fuchs WK, Rudnick EM, Chakravarty S, Patel JH (1995) Rapid diagnostic fault simulation of stuck-at faults in sequential circuits using compact lists. In: Proc. design automation conference, pp 133–138

  48. Wang Z, Marek-Sadowska M, Tsai K-H, Rajski J (2003) Multiple fault diagnosis using n-detection tests. In: Proc. 21st international conference on computer design, pp 198–201

  49. Wang Z, Marek-Sadowska M, Tsai K-H, Rajski J (2006) Analysis and methodology for multiple-fault diagnosis. IEEE Trans Comput-Aided Des 25 (3):558–575

    Article  Google Scholar 

  50. Yu X, Amyeen ME, Venkataraman S, Guo R, Pomeranz I (2003) Concurrent execution of diagnostic fault simulation and equivalence identification during diagnostic test generation. In: Proc. 21st IEEE VLSI test symp., pp 351–356

  51. Yu X, Wu J, Rudnick EM (2000) Diagnostic test generation for sequential circuits. In: Proc. international test conf., pp 225–234

  52. Zhang Y (2012) Diagnostic test pattern generation and fault simulation for stuck-at and transition faults. PhD thesis, Auburn University, ECE Dept.

  53. Zhang Y, Agrawal V D (2010) A diagnostic test generation system. In: Proc. international test conf., pp 360–368

  54. Zhang Y, Agrawal VD (2010) An algorithm for diagnostic fault simulation. In: Proc. 11th IEEE Latin American test workshop, pp 1–5

  55. Zhang Y, Agrawal VD (2011) Reduced complexity test generation algorithms for transition fault diagnosis. In: Proc. 29th IEEE international conf. computer design, pp 96–101

Download references

Acknowledgments

Research supported in part by the National Science Foundation Grants CNS-0708962 and CCF-1116213. Y. Zhang is with Broadcom Corporation, San Diego, CA 92127, USA.

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Auburn University, Auburn, AL, 36849, USA

    Yu Zhang, Bei Zhang & Vishwani D. Agrawal

Authors
  1. Yu Zhang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Bei Zhang
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Vishwani D. Agrawal
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Bei Zhang.

Additional information

Responsible Editor: M. Tehranipoor

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Zhang, Y., Zhang, B. & Agrawal, V.D. Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools. J Electron Test 30, 763–780 (2014). https://doi.org/10.1007/s10836-014-5490-4

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-014-5490-4

Keywords

Search

Navigation