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False Error Vulnerability Study of On-line Soft Error Detection Mechanisms

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Abstract

With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the Double Sampling checker (used in Razor), is the simplest and most area and power efficient, but suffers from very high false detection rates of 1.15 times higher than the actual error rates. We also find that the alternate approaches of Triple Sampling and Integrate & Sample method can be designed to have zero false detection rates, but at an increased area, power and implementation complexity. The Triple Sampling method has about 1.74 times the area and 1.83 times the power as compared to the Double Sampling method and also needs a complex clock generation scheme. The Integrate & Sample method needs about 6% more power and is 0.58 times the area of Double Sampling. It comes with more stringent implementation constraints as it requires detection of small voltage swings. We also analyse for Double Transient Faults (DTFs) and show that all the methods are prone to DTFs, with Integrate & Sample method being more vulnerable.

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References

  1. Baumann R (2001) Soft errors in advanced semiconductor devices part I: the three radiation sources. IEEE Trans Device Mater Reliab 1:17–22

    Article  Google Scholar 

  2. Blaauw D, Kalaiselvan S, Lai K, Ma WH, Pant S, Tokunaga C, Das S, Bull D (2008) Razor II: in situ error detection and correction for PVT and SER tolerance. In: IEEE international solid-state circuits conference

  3. Ernst D, Das S, Lee S, Blaauw D, Austin T, Mudge T, Kim NS, Flautner K (2003) Razor: circuit-level correction of timing errors for low-power operation. IEEE Micro 24(6):10–20

    Article  Google Scholar 

  4. Freeman LB (1996) Critical charge calculations for a bipolar SRAM array. IBM J Res Develop 40(1):119–129

    Article  Google Scholar 

  5. Harminder D, Sylvester D, Blaauw D (2005) Gate-level mitigation techniques for neutron-induced soft error rate. In: International symposium on quality electronic design, pp 175–180

  6. Hazucha P, Karnik T, Maiz J, Walstra S, Bloechel B, Tschanz J, Dermer G, Hareland S, Armstrong P, Borkar S (2003) Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation, international electron devices meeting, pp 523–526

  7. Kiran M, Amrutur B, Parekhji R (2008) False error study of on-line soft error detection mechanisms. In: International online testing symposium

  8. Kunal Ganeshpure AS, Kundu S (2007) On accelerating soft-error detection by targeted pattern generation, ISQED

  9. Lisboa CA, Kastensmidt FL, Henes Neto E, Wirth G, Carro L (2007) Using built-in sensors to cope with long duration transient faults in future technologies. In: Proc IEEE Int’l Test Conf, pp 1–10

  10. May TC, Woods MH (1979) Alpha-particle-induced soft error in dynamic memories. IEEE Trans Electron Devices 26(1):29

    Article  Google Scholar 

  11. Nicolidis M (1999) Time redundancy based soft error tolerance to rescue nanometer technologies. In: VLSI test symposium, pp 86–94

  12. Rossi D, Omana M, Metra C, Pagni A (2006) Checker no-harm alarm robustness. In: International online testing symposium, pp 10–12

  13. Satish Y, Amrutur B, Parekhji R (2007) Modified stability checking for on-line error detection. In: International conference on VLSI design, pp 787–792

  14. Seifert N, Slankard P, Kirsch M, Narasimham B, Zia V, Brookreson C, Vo A, Mitra S, Gill B, Maiz J (2006) Radiation induced soft error rates of advanced CMOS bulk devices. In: International reliability physics symposium, pp 217–225

  15. Shivakumar P, Kistler M, Keckler SW, Burger D, Alvisi L (2002) Modeling the effect of technology trends on the soft error rate of combinational logic. In: International conference on dependable systems and networks, pp 389–398

  16. Taber A, Normand E (1993) Single event upset in avionics. IEEE Trans Nucl Sci 40(2):120–125

    Article  Google Scholar 

  17. Tosaka Y, Kanata H, Satoh S, Itakura T (1999) Simple method for estimating neutron-induced soft error rates based on modified BGR Model. IEEE Electron Device Lett 20(2):89–91

    Article  Google Scholar 

  18. Tsiatouhas Y, Arapoyanni A, Nikolos D, Haniotakis Th (2002) A hierarchical architecture for concurrent soft error detection based on current sensing. International online testing workshop, p 56

  19. Ziegler JF, Curtis HW, Muhlfeld HP, Montrose CJ, Chin B (1996) IBM experiments in soft fails in computer electronics (1978–1994). IBM J Res Develop 40(1):3–18

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of ECE, IISc, Bangalore, India

    Kiran Kumar Reddy & Bharadwaj S. Amrutur

  2. Texas Instruments (India) Pvt. Ltd., Bangalore, India

    Rubin A. Parekhji

Authors
  1. Kiran Kumar Reddy
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  2. Bharadwaj S. Amrutur
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  3. Rubin A. Parekhji
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Corresponding author

Correspondence to Kiran Kumar Reddy.

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Responsible Editor: S. Kajihara

Appendix: Robust implementations of Integrate & Sample

Appendix: Robust implementations of Integrate & Sample

Using a sense amplifier with a fixed reference will not be practical in view of the variations in the Integrate & Sample cell. The solution to this is to generate a reference on-chip so that it can track the variations. Instead of using a constant Dummy line, the Dummy can be made to discharge at a rate which allows it to fall mid-way between the Sense voltages developed due to actual (sensea) and false (sensef) soft error cases as shown in Fig. 19. This can be achieved by using two Integrate & Sample cells, of half the width of that on the Sense line, onto the Dummy line with each having the integrating interval of δ max and Tstab eff as shown in Fig. 21. If I on is the on current of an Integrate & Sample cell of width W, then Integrate & Sample cell of width W/2 has an on current of approximately \(\frac{I_{on}}{2}\). In such a case using Eq. 4.2. The voltage across the Sense node for actual error is

$$ \label{eq:vsensea} \Delta V_{sensea}=\frac{I_{on}}{C_{int}} Tstab_{ef\/f} $$
(7.1)

Similarly, the voltage across the Sense node for false error is

$$ \label{eq:vsensef} \Delta V_{sensef}=\frac{I_{on}}{C_{int}} \delta_{max} $$
(7.2)

The voltage developed across Dummy node is given by

$$\begin{array}{lll} \label{eq:vdummy1} \Delta V_{dummy} &\sim& \frac{\frac{I_{on}}{2}}{C_{int}} Tstab_{ef\/f}+\frac{\frac{I_{on}}{2}}{C_{int}} \delta_{max} \\ &\sim& \frac{\Delta V_{sensef}+\Delta V_{sensea}}{2} \end{array}$$
(7.3)

The process of generation of Dummy reference level is explained in the Fig. 19. Figure 20 shows the working of Integrate & Sample method in case of a false error (Cycle 1) and an actual error (Cycle 2).

Fig. 19
figure 19

Generation of dummy reference level for Integrate & Sample method

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Fig. 20
figure 20

Actual and false errors in Integrate & Sample method

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In order to validate the correct working of the above explained behavior, the setup is analyzed using Monte Carlo simulation. The circuit is simulated by varying the process parameters like Vth (threshold Voltage), tox (oxide thickness), L (channel length) for all the transistors in the Integrate & Sample scheme and circuit parameters like C int (Table 4) The Fig. 21 shows the low margin (dummy-sensea) versus the high margin (sensef-dummy) simulated at four operating temperatures of 0°C, 27°C, 50°C, 100°C. Correct operation requires both these margins to remain positive. The sense amplifier outputs show the expected working of the Integrate & Sample method for the entire temperature range across all the MonteCarlo simulations (Fig. 22).

Table 4 Conditions for Monte Carlo simulation
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Fig. 21
figure 21

Reference generator for Integrate & Sample method shown in Fig. 6

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Fig. 22
figure 22

Margins in Integrate & Sample scheme, Monte Carlo simulations for worst case process for four different temperatures

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Reddy, K.K., Amrutur, B.S. & Parekhji, R.A. False Error Vulnerability Study of On-line Soft Error Detection Mechanisms. J Electron Test 26, 323–335 (2010). https://doi.org/10.1007/s10836-010-5153-z

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  • DOI: https://doi.org/10.1007/s10836-010-5153-z

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