Abstract
Hardware Transaction Memory (HTM) opens a new way to scaling multi-core software. Its main target is to achieve high performance on multi-core systems, and at the same time simplify concurrency control and guarantee correctness. This paper presents the redesign of an existing concurrent hash table using several HTM-based synchronization mechanisms. As compared with a fine-grained lock implementation, HTM-based locking scales well on our testing platform, and its performance is higher when running large-scale workloads. In addition, HTM-based global locking consumes much less memory. In summary, several observations are made in this paper with detailed experimental analysis, which would have important implications for future research of concurrent data structures and HTM.
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This research was supported in part by the National Science Foundation of China under Grants 61772183, 61572179 and 61272190.
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Chen, Z., He, X., Sun, J. et al. Have Your Cake and Eat it (Too): A Concurrent Hash Table with Hardware Transactions. Int J Parallel Prog 46, 699–709 (2018). https://doi.org/10.1007/s10766-017-0529-7
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DOI: https://doi.org/10.1007/s10766-017-0529-7