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Generator of dynamically reconfigurable processor

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Abstract

In recent years, demand for field-programmable gate arrays (FPGAs) has increased significantly. Designed similarly to software, FPGAs opened the door to the field of hardware for many people. However, developing a circuit using conventional methods is time consuming. In this paper, we propose a processor generator that can shorten development time and implement a dynamically reconfigurable architecture. This architecture is advantageous in comparison with other processor generators. With this architecture, our processor generator significantly reduces circuit scale, with the following reduction rates for each part of a 16-bit processor: 10.7, 6.2, 11.7, and 14.3 % for slices, flip-flops, look-up tables, and multipliers, respectively.

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References

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Acknowledgments

This work was supported by Tokyo Denki University Science Promotion Fund (Q12 J-03).

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Authors and Affiliations

  1. Graduate School of Engineering, Tokyo Denki University, 5 Senjyu-Asahi-cho, Adachi-ku, Tokyo, 120-8551, Japan

    Takahiko Sega, Akinori Kanasugi & Ki Ando

Authors
  1. Takahiko Sega
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  2. Akinori Kanasugi
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  3. Ki Ando
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Corresponding author

Correspondence to Ki Ando.

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Cite this article

Sega, T., Kanasugi, A. & Ando, K. Generator of dynamically reconfigurable processor. Artif Life Robotics 20, 103–108 (2015). https://doi.org/10.1007/s10015-015-0212-2

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  • DOI: https://doi.org/10.1007/s10015-015-0212-2

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