A systematic incrementalization technique and its application to hardware design

A systematic transformation method based on incrementalization and value caching generalizes a broad family of program optimizations. It yields significant performance improvements in many program classes, including iterative schemes that characterize hardware specifications. CACHET is an interactive incrementalization tool. Although incrementalization is highly structured and automatable, better results are obtained through interaction, where the main task is to guide term rewriting based on data-specific identities. Incrementalization specialized to iteration corresponds to strength reduction, a familiar program improvement technique. This correspondence is illustrated by the derivation of a hardware-efficient nonrestoring square-root algorithm, which has also served as an example of theorem prover-based implementation verification.

Authors and Affiliations

1. Indiana University Computer Science Department, Indiana University, Indiana, USA; E-mail: sjohnson@cs.indiana.edu, , , , , , US

   Steven D. Johnson

2. Computer Science Department, State University of New York at Stony Brook, New York, USA; E-mail: liu@cs.sunysb.edu, , , , , , US

   Yanhong A. Liu

3. Motorola Corp., Schaumburg, Illinois, USA, , , , , , US

   Yuchen Zhang

Published online: 9 October 2001

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ID="*"S.D. Johnson supported, in part, by the National Science Foundation under grant MIP-9601358.

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ID="**"Y.A. Liu supported in part by the National Science Foundation under grant CCR-9711253, the Office of Naval Research under grant N00014-99-1-0132, and Motorola Inc. under a Motorola University Partnership in Research Grant.

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ID="***"Y. Zhang is a student recipient of a Motorola University Partnership in Research Grant.

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