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Energy reduction in 3D NoCs through communication optimization

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Abstract

Network-on-Chip (NoC) architectures and three-dimensional (3D) integrated circuits have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. Specifically, on a heterogeneous 3D NoC architecture, we explore how different types of processors can be optimally placed to minimize data access costs. Moreover, we select the optimal set of links with optimal voltage levels. The experimental results indicate significant savings in energy consumption across a wide range of values of our major simulation parameters.

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References

  1. ITRS (2013) International technology roadmap for semiconductors

  2. Pavlidis V, Friedman E (2007) 3-d Topologies for networks-on-chip. Very large scale integration (VLSI) systems. IEEE Trans On 15(10):1081–1090

    Google Scholar 

  3. Davis W, Wilson J, Mick S, Xu J, Hua H, Mineo C, Sule A, Steer M, Franzon P (2005) Demystifying 3d ics: the pros and cons of going vertical. Design Test Comput IEEE 22(6):498–510

    Article  Google Scholar 

  4. Li F, Nicopoulos C, Richardson T, Xie Y, Narayanan V, Kandemir M (2006) Design and management of 3d chip multiprocessors using network-in-memory. In: Computer architecture, 2006. ISCA ’06. 33rd international symposium on, pp 130–141

  5. Murali S, Benini L, De Micheli G (2010) Design of networks on chips for 3d ics. In: Proceedings of the 2010 Asia and South Pacific design automation conference, pp 167–168

  6. Park D, Eachempati S, Das R, Mishra AK, Xie Y, Vijaykrishnan N, Das CR (2008) Mira: a multi-layered on-chip interconnect router architecture. SIGARCH Comput Archit News 36:251–261

    Article  Google Scholar 

  7. Loi I, Angiolini F, Benini L (2008) Developing mesochronous synchronizers to enable 3d nocs. In: Design, automation and test in Europe, 2008. DATE ’08, pp 1414–1419

  8. Borkar S (2011) 3d integration for energy efficient system design. In: design automation conference (DAC), 2011 48th ACM/EDAC/IEEE, pp 214–219

  9. Vivet P, Dutoit D, Thonnart Y, Clermidy F (2011) 3d NoC using through silicon via: an asynchronous implementation. In: VLSI and system-on-chip (VLSI-SoC), 2011 IEEE/IFIP 19th international conference on, pp 232–237

  10. Ebrahimi M, Daneshtalab M, Liljeberg P, Plosila J, Tenhunen H (2013) Cluster-based topologies for 3d networks-on-chip using advanced inter-layer bus architecture. J Comput Syst Sci 79(4):475–491

    Article  MATH  MathSciNet  Google Scholar 

  11. Daneshtalab M, Ebrahimi M, Plosila J (2012) Hibs: novel inter-layer bus structure for stacked architectures. In: 3D systems integration conference (3DIC), 2011 IEEE, international, pp 1–7

  12. Coskun AK, Ayala JL, Atienza D, Rosing TS, Leblebici Y (2009) Dynamic thermal management in 3d multicore architectures. DATE 1410–1415

  13. Akbari S, Shafiee A, Fathy M, Berangi R (2012) Afra: a low cost high performance reliable routing for 3d mesh nocs. DATE 332–337

  14. Wu TH, Davoodi A, Linderoth JT (2009) Grip: scalable 3d global routing using integer programming. DAC 320–325

  15. Ozturk O, Wang F, Kandemir M, Xie Y (2006) Optimal topology exploration for application-specific 3d architectures. In: Design automation, 2006. Asia and South Pacific conference on (2006)

  16. Akturk I, Ozturk O (2013) Ilp-based communication reduction for heterogeneous 3d network-on-chips. PDP 514–518

  17. Soteriou V, Peh LS (2004) Design-space exploration of power-aware on/off interconnection networks. In: Computer design: VLSI in computers and processors, 2004. ICCD 2004. Proceedings. IEEE international conference on, pp 510–517

  18. XPressMP (2008) FICO XPress optimization suite, http://www.fico.com/en/Products/DMTools/Pages/FICO-Xpress-Optimization-Suite.aspx

  19. Hu J, Shin Y, Dhanwada N, Marculescu R (2004) Architecting voltage islands in core-based system-on-a-chip designs. In: Low power electronics and design, 2004. ISLPED ’04. Proceedings of the 2004 international symposium on, pp 180–185

  20. Amarasinghe SP, Anderson JM, Lam MS, wen Tseng C (1993) An overview of the suif compiler for scalable parallel machines. In: Proceedings of the seventh SIAM conference on parallel processing for scientific computing, pp 662–667

  21. Wang HS, Zhu X, Peh LS, Malik S (2002) Orion: a power-performance simulator for interconnection networks. In: Microarchitecture, 2002. (MICRO-35). Proceedings 35th annual IEEE/ACM international symposium on, pp 294–305. doi:10.1109/MICRO.2002.1176258

  22. Chen G, Li F, Kandemir M (2006) Compiler-directed channel allocation for saving power in on-chip networks. SIGPLAN Not 41(1):194–205. doi:10.1145/1111320.1111055

    Article  Google Scholar 

  23. Chen G, Li F, Kandemir M, Irwin MJ (2006) Reducing NoC energy consumption through compiler-directed channel voltage scaling. SIGPLAN Not 41(6):193–203. doi:10.1145/1133255.1134004

    Article  Google Scholar 

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Author information

Authors and Affiliations

  1. Computer Engineering Department, Bilkent University, Ankara, Turkey

    Ozcan Ozturk

  2. Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, USA

    Ismail Akturk

  3. Computer Engineering Department, Canakkale Onsekiz Mart University, Çanakkale, Turkey

    Ismail Kadayif

  4. Computer Engineering Department, Ankara University, Ankara, Turkey

    Suleyman Tosun

Authors
  1. Ozcan Ozturk
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  2. Ismail Akturk
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  3. Ismail Kadayif
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  4. Suleyman Tosun
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Corresponding author

Correspondence to Ozcan Ozturk.

Additional information

This research is supported in part by TUBITAK grants 112E360 and 113E258, by a grant from Intel Corporation.

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Ozturk, O., Akturk, I., Kadayif, I. et al. Energy reduction in 3D NoCs through communication optimization. Computing 97, 593–609 (2015). https://doi.org/10.1007/s00607-013-0378-1

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