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A hardware oriented fuzzification algorithm and its VLSI implementation

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Abstract

An efficient fuzzification algorithm named as Dynamic Precision Fuzzification (DPF) is introduced in this paper which is mainly developed for hardware implementation. The DPF which might be generally used with any piecewise linear membership function, exploits an inherent capacity of the normal fuzzification algorithm to improve its efficiency when realized in a finite-precision implementation bed such as digital VLSI. The accuracy simulation results of the DPF and normal fuzzification method are presented and compared to show the superiority of the DPF. As the word-length is the most important parameter in a finite-precision implementation environment which determines the system cost-precision trade-off, the simulation results show that DPF provides suitable precision improvements with respect to traditional fuzzification without increasing the system word-length. The VLSI synthesis results of both methods are also presented to show that this considerable accuracy improvement is achieved by an acceptable increase in its VLSI implementation costs in terms of area, delay, and power consumption with respect to traditional methods.

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Authors and Affiliations

  1. Department of Computer and Electrical Engineering, Qazvin Azad University, Qazvin, Iran

    Mohammad Haji Seyed Javadi & Esmaeil Zeinali Kh

  2. ECE Department, Sh. Abbaspour University of Technology, Tehran, Iran

    Hamid Reza Mahdiani

Authors
  1. Mohammad Haji Seyed Javadi
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  2. Hamid Reza Mahdiani
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  3. Esmaeil Zeinali Kh
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Correspondence to Hamid Reza Mahdiani.

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Haji Seyed Javadi, M., Mahdiani, H.R. & Zeinali Kh, E. A hardware oriented fuzzification algorithm and its VLSI implementation. Soft Comput 17, 683–690 (2013). https://doi.org/10.1007/s00500-012-0940-3

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