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The Data Flow and Architectural Optimizations for a Highly Efficient CNN Accelerator Based on the Depthwise Separable Convolution

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Abstract

This paper presents the design and implementation of a convolutional neural network (CNN) accelerator for embedded and edge computing systems. To be specific, a novel processing flow is proposed in this paper so that the data that is already stored in the accelerator is maximally reused. This greatly reduces the requirements for the on-chip storage elements and the accesses to the off-chip memory. Therefore, significant reductions in the memory-access delay and the area complexity can be achieved. Based on the proposed data processing flow, a highly efficient VLSI architecture is designed and implemented. This architecture is based on a pipelined structure and maximizes the efficiency for the utilizations of hardware components. The implemented circuit is synthesized and placed- and routed with TSMC 90 nm technology, and the evaluations for the performance and area complexity are conducted based on the post-layout estimations. The experimental results show that the proposed CNN accelerator achieves a throughput of 44.06 Giga-MAC/s with the complexity of 5909KGEs. Furthermore, this design leads to a performance of 79.1 frame-per-second (fps) under the frequency of 250 MHz. Compared to the state-of-the-art accelerators, the proposed architecture achieves a significant enhancement in efficiency.

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Data Availability

The datasets generated and/or analyzed during the current study are available from the corresponding author on reasonable request.

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Acknowledgements

This work is supported in part by the Ministry of Science and Technology, Taiwan under grants MOST 109-2221-E-011-142 and 110-2221-E-011-155. The authors would like to thank Prof. Gerd Ascheid and Dr. Andreas Bytyn of RWTH Aachen University for their valuable inputs regarding the design of CNN accelerator.

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  1. Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan

    Hung-Ju Lin & Chung-An Shen

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  1. Hung-Ju Lin
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Correspondence to Chung-An Shen.

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Lin, HJ., Shen, CA. The Data Flow and Architectural Optimizations for a Highly Efficient CNN Accelerator Based on the Depthwise Separable Convolution. Circuits Syst Signal Process 41, 3547–3569 (2022). https://doi.org/10.1007/s00034-022-01952-5

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