Abstract
Time skew in time-interleaved ADCs (TI-ADCs) degrades the system’s linearity significantly.To address this problem, a time skew calibration method is proposed here that employs the divided clock signal as calibration signal. The divided squared clock signal containing a limited number of harmonics is demonstrated to be effective to extract the time skew, which is detected by comparing the estimated mean value of the product of two adjacent channels’ signals without extra reference ADC channel. The extracted time skew is subsequently compensated by a capacitor array-based digitally controlled delay block. Simulation results of a 4-channel 1GS/s 12-bit TI-ADC design demonstrated that the proposed calibration technique improved the spurious-free dynamic range of the ADC to 77 dB with a digitally controlled delay block that offers a time tuning resolution of 0.2 ps.
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Appendix
Appendix
Here, we derive the relation between time skew \(\Delta t_{m,m+1}\) and \(M_{m,m+1}\), which is the multiplication of digital outputs of each two adjacent channels. The digitized outputs x[n] are derived in Eq. (2). To observe the effect of offset and gain mismatch on time skew estimation, we introduce the offset mismatch \(b_{m}\) and gain mismatch \(a_{m}\) into Eq. (2); therefore,
The multiplication of mth and \(m+1\)th channel outputs is
where \(\Delta t_{m,m+1}\) is the time skew between channel m and channel \(m+1\), and M is the number of channels. \(e_{\mathrm{B}}[n]\) indicates the components related to zero-mean quantization noise \(q_{\mathrm{B}}[n]\). o[n] represents the components related to n. In Eq. (11), the gain mismatch \(a_{m}\) will affect the time skew estimation. However, from Fig. 4, if the \(f_{0}\) is selected close to \(f_{\mathrm{s}}\), the estimation value approximates to zero, which means the effect of gain mismatch is limited. Also, the effect of offset mismatch \(b_{m}\) is negligible for time skew calibration.
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Qiu, L., Zheng, Y. & Siek, L. Multichannel Time Skew Calibration for Time-Interleaved ADCs Using Clock Signal. Circuits Syst Signal Process 35, 2669–2682 (2016). https://doi.org/10.1007/s00034-015-0177-3
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DOI: https://doi.org/10.1007/s00034-015-0177-3