Abstract
This paper proposes two efficient architectures for hardware implementation of the Advanced Encryption Standard (AES) algorithm. The composite field arithmetic for implementing SubBytes (S-box) and InvSubBytes (Inverse S-box) transformations investigated by several authors is used as the basis for deriving the proposed architectures. The first architecture for encryption is based on optimized S-box followed by bit-wise implementation of MixColumns and AddRoundKey and optimized Inverse S-box followed by bit-wise implementation of InvMixColumns and AddMixRoundKey for decryption. The proposed S-box and Inverse S-box used in this architecture are designed as a cascade of three blocks. In the second proposed architecture, the block III of the proposed S-box is combined with the MixColumns and AddRoundKey transformations forming an integrated unit for encryption. An integrated unit for decryption combining the block III of the proposed InvSubBytes with InvMixColumns and AddMixRoundKey is formed on similar lines. The delays of the proposed architectures for VLSI implementation are found to be the shortest compared to the state-of-the-art implementations of AES operating in non-feedback mode. Iterative and fully unrolled sub-pipelined designs including key schedule are implemented using FPGA and ASIC. The proposed designs are efficient in terms of Kgates/Giga-bits per second ratio compared with few recent state-of-the-art ASIC (0.18-μm CMOS standard cell) based designs and throughput per area (TPA) for FPGA implementations.
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Notes
The SubBytes and InvSubBytes implementation described here has been presented in TENCON 2009 [18].
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The authors wish to thank the anonymous reviewers for their useful comments which have enhanced the value of the paper.
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Appendix
Appendix
The expression for \(s'_{37}\) of the output of integrated unit for encryption is given as
The expression for \(r'_{37}\) of the output of integrated unit for decryption is given as
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Rachh, R.R., Mohan, P.V.A. & Anami, B.S. Efficient Implementations for AES Encryption and Decryption. Circuits Syst Signal Process 31, 1765–1785 (2012). https://doi.org/10.1007/s00034-012-9395-0
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DOI: https://doi.org/10.1007/s00034-012-9395-0