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A Low-Power Memory-Efficient Resampling Architecture for Particle Filters

  • Low Power Digital Filters
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Abstract

In this paper, we propose a compact threshold-based resampling algorithm and architecture for efficient hardware implementation of particle filters (PFs). By using a simple threshold-based scheme, this resampling algorithm can reduce the complexity of hardware implementation and power consumption. Simulation results indicate that this algorithm has approximately equal performance with the traditional systematic resampling (SR) algorithm when the root-mean-square error (RMSE) and lost track are considered. Experimental comparison of the proposed hardware architecture with those based on the SR and the residual systematic resampling (RSR) algorithms was conducted on a Xilinx Virtex-II Pro field programmable gate array (FPGA) platform in the bearings-only tracking context, and the results establish the superiority of the proposed architecture in terms of high memory efficiency, low power consumption, and low latency.

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Authors and Affiliations

  1. College of Information Science and Engineering, Zhejiang University, 38 Zheda Road, Hangzhou, Zhejiang, 310027, People’s Republic of China

    Shao-Hua Hong, Zhi-Guo Shi, Ji-Ming Chen & Kang-Sheng Chen

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  1. Shao-Hua Hong
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  2. Zhi-Guo Shi
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  3. Ji-Ming Chen
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  4. Kang-Sheng Chen
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Correspondence to Zhi-Guo Shi.

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Hong, SH., Shi, ZG., Chen, JM. et al. A Low-Power Memory-Efficient Resampling Architecture for Particle Filters. Circuits Syst Signal Process 29, 155–167 (2010). https://doi.org/10.1007/s00034-009-9117-4

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  • DOI: https://doi.org/10.1007/s00034-009-9117-4

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