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Design of configurable I/O pin control block for improving reusability in multimedia SoC platforms

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Abstract

Multimedia system-on-a-chip (SoC) platform designs nowadays are facing some conflicting issues regarding product development. One is induced by increasing design complexity and another is induced by decreasing time-to-market. Hence, designers are seeking a more efficient and reliable methodology in order to design complex multi-million gate SoC under such harsh conditions. In particular, the complexity of a generic pin control block in multimedia SoC which implements input/output (I/O) paths for off-chip communication has increased exponentially in recent years. Accordingly, the possibility of introducing human errors in designing such block has grown. Operation of generic-pin control block needs to be validated with a top-level RTL from the early stages of design, which correctly checks full-chip interface. However, generic-pin control block has inherent several design issues since function registers and multi-I/O paths are usually fixed in the relatively late stages of design. Also, the role of a generic pin control block that shares limited pins causes frequent changes in pin assignment. Therefore, current design approaches of a generic pin control block are no longer adequate to meet the challenges of design productivity, design reusability, and shorter time-to-market for design. And, this results in many possible human errors when using a traditional RTL description. As a response to this problem, this paper presents a design automation based approach to reduce the possibility of human errors. In the case study presented, we succeeded in auto-generating a generic pin control block in multimedia SoC platforms which has more than 300 general purpose I/O interfaces including both input and output, as well as 900 PAD pins. Ultimately, we reduced the amount of manual description for generating a generic pin control block by a whopping 97 %.

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Authors and Affiliations

  1. Department of EECS, The Henry Samueli School of Engineering, University of California, Irvine, CA, USA

    Myoung-Seo Kim & Jean-Luc Gaudiot

  2. Department of Computer Science, Namseoul University, Cheonan, Choongnam, South Korea

    Cheong Ghil Kim

  3. Department of Computer Science, Yonsei University, Seoul, South Korea

    Shin-Dug Kim

Authors
  1. Myoung-Seo Kim
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  2. Cheong Ghil Kim
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  3. Shin-Dug Kim
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  4. Jean-Luc Gaudiot
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Correspondence to Myoung-Seo Kim.

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Kim, MS., Kim, C.G., Kim, SD. et al. Design of configurable I/O pin control block for improving reusability in multimedia SoC platforms. Multimed Tools Appl 74, 9055–9066 (2015). https://doi.org/10.1007/s11042-013-1598-2

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